Patents by Inventor Cesar Garza

Cesar Garza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230188086
    Abstract: A mounting bracket for a solar array includes a top hat assembly including an outer top hat having a longitudinally extending first rail configured to contact a solar module of the solar array, and an inner top having a longitudinally extending second rail also configured to contact the solar module, an actuator arm assembly comprising a pair of actuator arms which extend from the top hat assembly and which form an opening configured to receive a tubular member of the solar array, and a fastener assembly configured to connect the pair of actuator arms and secure the mounting bracket to both the solar module and the tubular member.
    Type: Application
    Filed: December 9, 2022
    Publication date: June 15, 2023
    Applicant: National Oilwell Varco, L.P.
    Inventors: Julio Cesar Garza, Adam Kim, Mitchell Benson, Travis Miller, Milos Stancic
  • Publication number: 20050224455
    Abstract: Photoresist, which contains hydrogen, is patterned over a semiconductor substrate then treated with either a molecular halogen or a liquid fluorinating agent in order to improve subsequent ion implantation. Hydrogen is replaced, to whatever extent is found desirable, with the halogen. Molecular fluorine (F2) has been found to be particularly effective as the molecular halogen. Molecular fluorine (F2) reacts very efficiently in replacing the hydrogen and further has the benefit of continuing to penetrate into the patterned photoresist so that the entire patterned photoresist layer can have the hydrogen atoms replaced with fluorine atoms if the molecular fluorine flow is continued long enough. The resulting treated photoresist is much more resistant to penetration by implanted ions so that the photoresist can be deposited to a lesser thickness. This is beneficial in shadowing problems such as can occur in halo implants and where the patterned photoresist has a high aspect ratio.
    Type: Application
    Filed: June 2, 2005
    Publication date: October 13, 2005
    Inventors: Patrick Montgomery, Cesar Garza, William Taylor
  • Publication number: 20050181630
    Abstract: A semiconductor device is made by patterning a conductive layer for forming gates of transistors. The process for forming the gates has a step of patterning photoresist that overlies the conductive layer. The patterned photoresist is trimmed so that its width is reduced. Fluorine, preferably F2, is applied to the trimmed photoresist to increase its hardness and its selectivity to the conductive layer. Using the trimmed and fluorinated photoresist as a mask, the conductive layer is etched to form conductive features useful as gates. Transistors are formed in which the conductive pillars are gates. Other halogens, especially chlorine, may be substituted for the fluorine.
    Type: Application
    Filed: February 13, 2004
    Publication date: August 18, 2005
    Inventors: Cesar Garza, William Darlington, Stanley Filipiak, James Vasek
  • Publication number: 20050026084
    Abstract: A semiconductor device (10) includes a photoresist layer (20) for patterning features on the semiconductor device (10) during manufacturing. After the photoresist layer (20) is deposited, the semiconductor device (10) is exposed to fluorine using a fluorination module (126). In one embodiment, the fluorine is applied via a plasma in the fluorination module (126). In other embodiments, the fluorine may be applied in other gaseous or liquid forms. Fluorinating the photoresist layer (20) functions to prevent slimming of the features when dimensions of the features are measured using a scanning electron microscope (SEM).
    Type: Application
    Filed: July 31, 2003
    Publication date: February 3, 2005
    Inventors: Cesar Garza, Willard Conley, William Taylor
  • Patent number: 6649452
    Abstract: A lithographic reticle with subresolution features in the design-pattern is used to control critical dimensions in a semiconductor manufacturing process. After the location of design and processing features is determined, subresolution features are formed in areas devoid of design and processing features. The subresolution features can substantially fill all of the area devoid of design processing features or, instead, selectively fill portions of the area. In one embodiment, the width of the area devoid of design and processing features is less than two times the width of a feature. The presence of the subresolution features results in improved control of small dimensions of features in semiconductor processing, thereby increasing yield and device performance.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: November 18, 2003
    Assignee: Motorola, Inc.
    Inventors: Kevin D. Lucas, William L. Wilkinson, Cesar Garza
  • Publication number: 20030162329
    Abstract: A lithographic reticle with subresolution features in the design-pattern is used to control critical dimensions in a semiconductor manufacturing process. To determine the location of subresolution features the location of design and processing features is determined and the subresolution features are formed in areas devoid of design and processing features. The subresolution features can substantially fill all of the area devoid of design and processing features or, instead, selectively fill portions of the area. In one embodiment, the width of the area devoid of design and processing features is less than two times the width of a feature. The presence of the subresolution features results in improved control of small dimensions of features in semiconductor processing, thereby increasing yield and device performance.
    Type: Application
    Filed: February 28, 2002
    Publication date: August 28, 2003
    Inventors: Kevin D. Lucas, William L. Wilkinson, Cesar Garza
  • Patent number: 6593033
    Abstract: An embodiment of the instant invention is a mask having a pattern which is transferred to a layer overlying a semiconductor wafer, the mask comprising: a transmissive portion (structure 102 of FIG. 1), the transmissive portion allowing energy which impinges upon the transmission portion to substantially pass through the transmissive portion; a substantially non-transmissive portion (structure 106 of FIG. 1); a semi-transmissive portion (structure 104 of FIG. 1) situated between the transmissive portion and the substantially non-transmissive portion, energy passing through the semi-transmissive portion having a phase; and wherein the phase of energy which passes through the semi-transmissive portion is out of phase with the phase of energy which passes through the transmissive portion. Preferably, the phase of the energy which passes through the semi-transmissive portion is around 180 degrees out of phase with energy which passes through the transmissive portion.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: July 15, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Zhiliu Ma, Anthony Yen, Cesar Garza