Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of circuits for managing results from list decode methods. In accordance with some examples disclosed herein, a plurality of potential error patterns for correcting errors in a codeword may be received. The plurality of potential error patterns may be generated using a plurality of different list decode methods. Error patterns among the plurality of potential error patterns may be determined and marked as candidate error patterns using a set of error pattern screens. Error weights may be assigned to the candidate error patterns based on a quantity of bit errors in each symbol included therein. Weights for candidate error patterns that are indicative of a memory device failure may be adjusted using a scaling factor. An error pattern among the candidate error patterns may be selected to correct the errors in the codeword based on the assigned error weights.

Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of circuits for managing results from list decode methods. In accordance with some examples disclosed herein, a plurality of potential error patterns for correcting errors in a codeword may be received. The plurality of potential error patterns may be generated using a plurality of different list decode methods. Error patterns among the plurality of potential error patterns may be determined and marked as candidate error patterns using a set of error pattern screens. Error weights may be assigned to the candidate error patterns based on a quantity of bit errors in each symbol included therein. Weights for candidate error patterns that are indicative of a memory device failure may be adjusted using a scaling factor. An error pattern among the candidate error patterns may be selected to correct the errors in the codeword based on the assigned error weights.