Abstract: A system and method are disclosed for a flexible routing engine in a PCIe switch. The system may include a switch manager that is enabled, through firmware, to configure one or more routing tables associated with a switch stack of a PCIe switch. The method may include receiving a configuration transaction layer packet at the switch manager of a PCIe switch, running firmware at the switch manager to identify a desired behavior of a switch stack of the switch and updating one or more routing tables associated with switch stack.

Abstract: A system and method are disclosed for a flexible routing engine in a PCIe switch. The system may include a switch manager that is enabled, through firmware, to configure one or more routing tables associated with a switch stack of a PCIe switch. To enable non-transparent bridging and non-standard routing, the method may include receiving a transaction layer packet at a translated routing port of a PCIe switch, and performing translation of the address and requester ID of the packet utilizing tables that are updated by the firmware of the switch manager to route the packet through the switch.

Abstract: A peripheral component interconnect express (PCIe) switch includes non-transparent endpoints, each of which is associated with a bus hierarchy domain. A source non-transparent endpoint in a source bus hierarchy domain receives a packet including a destination address and identifies a destination bus hierarchy domain including a destination non-transparent endpoint based on the destination address. Further, the source non-transparent endpoint translates a requester identifier in the packet to a translated requester identifier and generates a translated request packet including the translated requester identifier. The PCIe switch routes the translated request packet to the destination non-transparent endpoint through a non-transparent interconnect in the PCIe switch. In this way, the PCIe switch interconnects multiple bus hierarchy domains and is non-transparent in the multiple bus hierarchy domains.

Abstract: In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.

Abstract: A processor access module receives a data command from an agent located externally of a computing processor and performs a cache operation on a cache memory in the computing processor based on the data command. Alternatively, the processor access module receives a data command from the agent and performs a cache operation on the cache memory based on the data command to store a computer program into the cache memory. The processor access module then receives a boot command from the agent and boots the computing processor to initiate execution of the computer program.

Abstract: An integrated circuit delay device includes a digital delay line configured to provide a percent-of-clock period delay to a timing signal received at an input thereof, in response to a control signal. This control signal has a value that specifies a length of the delay. A delay line control circuit is also provided. The delay line control circuit is configured to generate the control signal by counting multiple cycles of a high frequency oscillator signal (e.g., ring oscillator signal) having a period less than the clock period, over a time interval having a duration greater than the clock period.

Abstract: In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.

Abstract: Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments are described. A sample vector is characterized by bit locations corresponding to sequentially increasing delay values so that values stored in such bit locations indicate clock signal edges where value transitions occur. In one embodiment, edge detection logic and sensitivity adjustment logic are used in determining the clock period from such a sample vector. In another embodiment, an edge filter, sample accumulation logic, and clock period and jitter processing logic are used in determining an average clock period and clock jitter from a predefined number of such sample vectors.

Abstract: A computer system is provided that includes a direct memory access (DMA) controller, a memory control device and a slave device, all coupled to a system bus. The DMA controller is configured to implement fly-by read and fly-by write operations between the memory control device and the slave device. The memory control device and the slave device each include read and write aligners. During a fly-by read, data is read from slave device and aligned to the system bus using a peripheral read aligner. The memory control device re-aligns the data received on the system bus using a write aligner and writes the data to a main memory. During a fly-by write, data is read from the main memory and aligned to the system bus using a read aligner in memory control device. A write aligner in the slave device then re-aligns the data received on the system bus.

Abstract: An integrated circuit delay device includes a digital delay line configured to provide a percent-of-clock period delay to a timing signal received at an input thereof, in response to a control signal. This control signal has a value that specifies a length of the delay. A delay line control circuit is also provided. The delay line control circuit is configured to generate the control signal by counting multiple cycles of a high frequency oscillator signal (e.g., ring oscillator signal) having a period less than the clock period, over a time interval having a duration greater than the clock period.

Abstract: Integrated circuit delay devices include a digital delay line that is configured to provide a percent-of-clock period delay to a timing signal accepted at an enabled one of a plurality of injection ports thereof. The digital delay line may be responsive to an injection control signal having a value that sets a length of the delay by specifying a location of the enabled one of the plurality of injection ports, with the end of the delay line being a fixed output port. A delay line control circuit is also provided that is responsive to a clock signal having a period from which the percent-of-clock period delay is preferably measured. The delay line control circuit is configured to generate the injection control signal by counting multiple cycles of a high frequency ring oscillator signal having a period less than, and typically substantially less than, the clock period, over a time interval having a duration greater than, and typically substantially greater than, the clock period.

Abstract: Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments are described. A sample vector is characterized by bit locations corresponding to sequentially increasing delay values so that values stored in such bit locations indicate clock signal edges where value transitions occur. In one embodiment, edge detection logic and sensitivity adjustment logic are used in determining the clock period from such a sample vector. In another embodiment, an edge filter, sample accumulation logic, and clock period and jitter processing logic are used in determining an average clock period and clock jitter from a predefined number of such sample vectors.

Abstract: Integrated circuit delay devices include a digital delay line that is configured to provide a percent-of-clock period delay to a timing signal accepted at an enabled one of a plurality of injection ports thereof. The digital delay line may be responsive to an injection control signal having a value that sets a length of the delay by specifying a location of the enabled one of the plurality of injection ports, with the end of the delay line being a fixed output port. A delay line control circuit is also provided that is responsive to a clock signal having a period from which the percent-of-clock period delay is preferably measured. The delay line control circuit is configured to generate the injection control signal by counting multiple cycles of a high frequency ring oscillator signal having a period less than, and typically substantially less than, the clock period, over a time interval having a duration greater than, and typically substantially greater than, the clock period.

Abstract: An apparatus and method for generating a compensated percent-of-clock period delay signal are described. A first circuit determines how many delay elements a clock signal passes through during one period of the clock signal. A second circuit passes a signal to be delayed through the same number of delay elements according to information received from the first circuit. The ratio of the values of delay elements in the first and second circuits determines the percent-of-clock period that the passed signal is delayed. Since the clock signal is relatively insensitive to reference voltage and temperature variations as compared to the delay elements, the percent-of-clock period is maintained as more or less delay elements are passed through during a period of the clock signal.

Abstract: A system is provided that includes a bus master, a bus slave and a fly-by slave interface, all coupled to a peripheral bus. A peripheral device is coupled to the fly-by slave interface. The bus master is configured to control fly-by transfer of data between the bus slave and the peripheral device without buffering the data. The fly-by slave interface is configured to isolate the peripheral device from the peripheral bus during fly-by transfer of data between the bus slave and the peripheral device. In addiction, the bus slave is configured to provide a set of control signals on the peripheral bus, wherein the control signals regulate the flow of data on the peripheral bus during fly-by transfer of data between the bus slave and the peripheral device. Fly-by transfers can be fully synchronous, and burst operation at the rate of one data value per clock cycle is supported.

Abstract: A computer system is provided that includes a direct memory access (DMA) controller, a memory control device and a slave device, all coupled to a system bus. The DMA controller is configured to implement fly-by read and fly-by write operations between the memory control device and the slave device. The memory control device and the slave device each include read and write aligners. During a fly-by read, data is read from slave device and aligned to the system bus using a peripheral read aligner. The memory control device re-aligns the data received on the system bus using a write aligner and writes the data to a main memory. During a fly-by write, data is read from the main memory and aligned to the system bus using a read aligner in memory control device. A write aligner in the slave device then re-aligns the data received on the system bus.