Patents by Inventor Cesare Artoni

Cesare Artoni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7052985
    Abstract: A process forms an integrated device having: a first conductive region; a second conductive region; an insulating layer arranged between the first and the second conductive region; at least one through opening extending in the insulating layer between the first and the second conductive region; and a contact structure formed in the through opening and electrically connecting the first conductive region and the second conductive region. The contact structure is formed by a conductive material layer that coats the side surface and the bottom of the through opening and surrounds an empty region which is closed at the top by the second conductive region. The conductive material layer preferably comprises a titanium layer and a titanium-nitride layer arranged on top of one another.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: May 30, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Raffaele Zambrano, Cesare Artoni, Chiara Corvasce
  • Patent number: 7049646
    Abstract: A memory cell of a stacked type is formed by a MOS transistor and a ferroelectric capacitor. The MOS transistor is formed in an active region of a substrate of semiconductor material and comprises a conductive region. The ferroelectric capacitor is formed on top of the active region and comprises a first and a second electrodes separated by a ferroelectric region. A contact region connects the conductive region of the MOS transistor to the first electrode of the ferroelectric capacitor. The ferroelectric capacitor has a non-planar structure, formed by a horizontal portion and two side portions extending transversely to, and in direct electrical contact with, the horizontal portion.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: May 23, 2006
    Assignee: STMicroelectronics, S.R.L.
    Inventors: Raffaele Zambrano, Cesare Artoni
  • Publication number: 20040175927
    Abstract: A process forms an integrated device having: a first conductive region; a second conductive region; an insulating layer arranged between the first and the second conductive region; at least one through opening extending in the insulating layer between the first and the second conductive region; and a contact structure formed in the through opening and electrically connecting the first conductive region and the second conductive region. The contact structure is formed by a conductive material layer that coats the side surface and the bottom of the through opening and surrounds an empty region which is closed at the top by the second conductive region. The conductive material layer preferably comprises a titanium layer and a titanium-nitride layer arranged on top of one another.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 9, 2004
    Applicant: STMicroelectronics S.r.I.
    Inventors: Raffaele Zambrano, Cesare Artoni, Chiara Corvasce
  • Patent number: 6734565
    Abstract: An integrated device having: a first conductive region; a second conductive region; an insulating layer arranged between the first and the second conductive region; at least one through opening extending in the insulating layer between the first and the second conductive region; and a contact structure formed in the through opening and electrically connecting the first conductive region and the second conductive region. The contact structure is formed by a conductive material layer that coats the side surface and the bottom of the through opening and surrounds an empty region which is closed at the top by the second conductive region. The conductive material layer preferably comprises a titanium layer and a titanium-nitride layer arranged on top of one another.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: May 11, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Raffaele Zambrano, Cesare Artoni, Chiara Corvasce
  • Publication number: 20030146460
    Abstract: A memory cell of a stacked type is formed by a MOS transistor and a ferroelectric capacitor. The MOS transistor is formed in an active region of a substrate of semiconductor material and comprises a conductive region. The ferroelectric capacitor is formed on top of the active region and comprises a first and a second electrodes separated by a ferroelectric region. A contact region connects the conductive region of the MOS transistor to the first electrode of the ferroelectric capacitor. The ferroelectric capacitor has a non-planar structure, formed by a horizontal portion and two side portions extending transversely to, and in direct electrical contact with, the horizontal portion.
    Type: Application
    Filed: December 20, 2002
    Publication date: August 7, 2003
    Applicant: STMicroelectronics S.r.I
    Inventors: Raffaele Zambrano, Cesare Artoni
  • Publication number: 20020180054
    Abstract: An integrated device having: a first conductive region; a second conductive region; an insulating layer arranged between the first and the second conductive region; at least one through opening extending in the insulating layer between the first and the second conductive region; and a contact structure formed in the through opening and electrically connecting the first conductive region and the second conductive region. The contact structure is formed by a conductive material layer that coats the side surface and the bottom of the through opening and surrounds an empty region which is closed at the top by the second conductive region. The conductive material layer preferably comprises a titanium layer and a titanium-nitride layer arranged on top of one another.
    Type: Application
    Filed: April 18, 2002
    Publication date: December 5, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Raffaele Zambrano, Cesare Artoni, Chiara Corvasce