Abstract: A controller is provided for a baseband switching matrix with one space switching stage. The matrix supplies the controller with a number of service channels (IOTS, CH) of the uplink frames, which channels comprise encoded commands that are decoded by the controller which generates service channels (IOTD, FMC) for the downlink frames and sends them towards the matrix. The controller is subdivided into three functional units: a preprocessing unit (PREL) which decodes uplink frame service channels; a processing unit (ELAB), which receives the commands decoded by the preprocessing unit and/or by a telecontrol station with which it performs a bidirectional dialogue and generates control signals comprising the matrix switching states; and an interface unit (INTM) comprising two memories (MEMA, MEMB) alternatively operating as active or backup memory, which store the switching states supplied by the processing unit and send them to the matrix.

Abstract: An interface facilitating data transmission between a control processor, connected to an asynchronous two-way bus, and a plurality of terminals, connected to a common synchronous two-way bus, comprises a microprocessor responsive to periodically recurring access requests from the several terminals. The access requests are short pulses with a recurrence period greatly exceeding their duration, this period being nominally equal for all terminals and sufficient to accommodate one data transfer to or from each terminal with time remaining for execution of part of a main program performed by the control processor. Coinciding access requests from different terminals are handled according to a predetermined order of priority. The exchange of data takes place by way of a data memory and a buffer memory linked by an internal two-way bus. Data transfer between the control processor and a terminal takes place in three stages, i.e.

Abstract: Television signals generated at a transmitting station are digitized and are then transformed into bit groups by a precoder reducing their information content by eliminating redundancies, as by comparing each pixel of a given frame with the homologous pixel of the immediately preceding frame and, upon detecting their equality, emitting a particular reduction code in lieu of an otherwise emitted luminance signal. A message encoder following the precoder generates outgoing data words which may comprise a luminance value accompanied by an integrity code, a changeover signal accompanied by a reduction code, a numerical value specifying the number of consecutive pixels remaining unchanged from the preceding frame, or a synchronizing code. The bits of the outgoing data words are serialized and are temporarily stored in a buffer register in order to be sent at regular intervals, via a communication channel, to a receiving station where a message decoder regroups them in their original order.

Abstract: An SS/TDMA communication system comprises a multiplicity of ground stations, including one master station and a number of traffic stations without control function, exchanging digitized voice or other message signals via a relay station aboard a satellite. Each ground station comprises base-band equipment including a transmitting section, a receiving section and a control unit. The control unit of the master station generates outgoing timing signals and processes incoming timing signals for synchronizing the operations of its own equipment and that of the traffic stations with the operation of a switching unit of the satellite-borne relay station; this control unit also emits routing instructions for that switching unit.

Abstract: A system for the exchange of messages among a multiplicity of processing units includes a data channel and a service line interconnecting respective interfaces of these units. Each interface includes a busy-state detector determining during a test phase of a recurrent time slot whether the service line is available, a logic network connectable in a subsequent acquisition phase the service line in the event of its availability to emit successive bits of an address characterizing the respective processing unit, and a comparator determining during the aquisition phase whether an emitted address bit of a particular logic level ("1") coincides with another bit of a higher-priority level ("0") concurrently sent over the line by some other unit. If a higher-priority address bit is encountered, the emission of the address is aborted and restarted in a subsequent time slot.

Abstract: A central processor controlling a set of peripheral units through an associated logic network is programmed to activate from time to time, through a direct connection by-passing the logic network, a checking unit including a read-only memory storing a variety of microprograms in areas individually addressable by the processor. Upon the reception of a memory address, a timing circuit is set to determine the frequency of stepping pulses advancing a counter which calls forth successive phases of the selected mircroprogram. Code words read out during these phases to the logic network are fed back by the latter to the processor for comparison with corresponding contents of its own program memory; in the event of a disparity, or when failure of the processor to emit a resetting signal lets the counter advance to the limit of its capacity, an alarm indicator is tripped.