Abstract: A method is for implementing at least one clock tree in a synchronous digital electronic circuit. The method may include selecting an interchangeable programmable delay buffer stage, calculating an expected skew based upon the selected interchangeable programmable delay buffer stage, and interchanging the selected interchangeable programmable delay buffer stage with another if the expected skew is different from a desired skew. A related synchronous digital electronic circuit includes a plurality of clock trees, and an interchangable programmable delay buffer stage connected to each of the clock trees.

Abstract: The method relates to assembling modules for an integrated circuit comprising at least a plurality of modules. The method provides for the formation of at least one module architecture which comprises a plurality of modules and is aligned along one dimension of such modules. The invention also concerns an integrated circuit and a stacked module architecture obtained with the inventive assembling method.

Abstract: A complex integrated circuit comprises at least a plurality of modules coupled together through at least a system channel. The circuit further comprises a plurality of input/output devices for interfacing the circuit with structures outside the circuit. The plurality of input/output devices comprise at least a first circuit portion implemented as a module coupled to the remaining modules of the circuit by the first channel system (BUS1).