Abstract: A photonic semiconductor device and method are provided that ensure that the surface of the device upon completion of the SAG process is planar, or at least substantially planar, such that performance of the subsequent processes is facilitated, thereby enabling higher manufacturing yield to be achieved. A photonic semiconductor device and method are also provided that ensure that the isolation region of the device will have high resistance and low capacitance, without requiring the placement of a thick dielectric material beneath each of the contact pads. Eliminating the need to place thick dielectric materials underneath the contact pads eliminates the risk that the contact pads will peel away from the assembly.

Abstract: An integrated device includes two sections (A, B), such as a DFB laser (A) and an EAM modulator (B), having a semi-insulating (SI) separation region therebetween. The separation region (24) is of a material acting as a trap on electrons and configured to impede current flow between the two sections (A, B) due to holes. The separation region (24) may be of a material acting as a trap both on electrons and holes. Alternatively, the separation region (24) is of a material that acts as a trap on electrons and is provided over a p-type substrate (20) common to the two sections (A, B).

Abstract: A photonic semiconductor device and method are provided that ensure that the surface of the device upon completion of the SAG process is planar, or at least substantially planar, such that performance of the subsequent processes is facilitated, thereby enabling higher manufacturing yield to be achieved. A photonic semiconductor device and method are also provided that ensure that the isolation region of the device will have high resistance and low capacitance, without requiring the placement of a thick dielectric material beneath each of the contact pads. Eliminating the need to place thick dielectric materials underneath the contact pads eliminates the risk that the contact pads will peel away from the assembly.

Abstract: A photonic semiconductor device and method are provided that ensure that the surface of the device upon completion of the SAG process is planar, or at least substantially planar, such that performance of the subsequent processes is facilitated, thereby enabling higher manufacturing yield to be achieved. A photonic semiconductor device and method are also provided that ensure that the isolation region of the device will have high resistance and low capacitance, without requiring the placement of a thick dielectric material beneath each of the contact pads. Eliminating the need to place thick dielectric materials underneath the contact pads eliminates the risk that the contact pads will peel away from the assembly.

Abstract: A photonic semiconductor device and method are provided that ensure that the surface of the device upon completion of the SAG process is planar, or at least substantially planar, such that performance of the subsequent processes is facilitated, thereby enabling higher manufacturing yield to be achieved. A photonic semiconductor device and method are also provided that ensure that the isolation region of the device will have high resistance and low capacitance, without requiring the placement of a thick dielectric material beneath each of the contact pads. Eliminating the need to place thick dielectric materials underneath the contact pads eliminates the risk that the contact pads will peel away from the assembly.

Abstract: An integrated device includes two sections (A, B), such as a DFB laser (A) and an EAM modulator (B), having a semi-insulating (SI) separation region therebetween. The separation region (24) is of a material acting as a trap on electrons and configured to impede current flow between the two sections (A, B) due to holes. The separation region (24) may be of a material acting as a trap both on electrons and holes. Alternatively, the separation region (24) is of a material that acts as a trap on electrons and is provided over a p-type substrate (20) common to the two sections (A, B).

Abstract: An integrated device includes two sections, such as a DFB laser and an EAM modulator, having a semi-insulating separation region therebetween. The separation region is of a material acting as a trap on electrons and configured to impede current flow between the two sections due to holes. The separation region may be of a material acting as a trap both on electrons and holes. Alternatively, the separation region is of a material that acts as a trap on electrons and is provided over a p-type substrate common to the two sections.

Abstract: Integrated semiconductor devices are manufactured by providing a layered semiconductor structure having an exposed surface and providing a mask on the exposed surface thereby defining a masked region in the layered structure underneath said mask. The mask has a main direction of extension with a width across the main direction and an end portion. The layered structure is etched over a given depth starting from the exposed surface, whereby the masked region is left substantially unaffected by the etching process and has an end surface extending underneath the end portion of the mask. A further layered semiconductor structure is grown around the masked region to produce an integrated layered semiconductor structure having at the end surface an interface between the layered structure and the further grown structure. The mask width is selected to be less than 50 microns.

Abstract: Integrated semiconductor devices are manufactured by providing a layered semiconductor structure having an exposed surface and providing a mask on the exposed surface thereby defining a masked region in the layered structure underneath said mask. The mask has a main direction of extension with a width across the main direction and an end portion. The layered structure is etched over a given depth starting from the exposed surface, whereby the masked region is left substantially unaffected by the etching process and has an end surface extending underneath the end portion of the mask. A further layered semiconductor structure is grown around the masked region to produce an integrated layered semiconductor structure having at the end surface an interface between the layered structure and the further grown structure. The mask width is selected to be less than 50 microns.