Patents by Inventor Cezar Bogdan Zota
Cezar Bogdan Zota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11816062Abstract: The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.Type: GrantFiled: November 4, 2021Date of Patent: November 14, 2023Assignee: International Business Machines CorporationInventors: Thomas Morf, Cezar Bogdan Zota, Peter Mueller, Pier Andrea Francese, Marcel A. Kossel, Matthias Braendli, Mridula Prathapan
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Patent number: 11756837Abstract: A method forms heterogeneous complementary FETs and a related semiconductor structure. The method comprises forming a layered nanosheet stack comprising two layers of a first channel material alternating with two layers of a second channel material, depositing a dielectric layer on a top layer of the nanosheet stack, and forming a checkered mask material with at least a first and a second row above the dielectric material. The first and the second row are distanced from each other. The method removes the first channel material and the second channel material outside an area of the checkered mask material, resulting in the at least a first row of pillars and a second row of pillars of layered nanosheet stacks. The method selectively removes in each of the pillars of the first stripe the second channel material.Type: GrantFiled: March 17, 2021Date of Patent: September 12, 2023Assignee: International Business Machines CorporationInventors: Cezar Bogdan Zota, Clarissa Convertino, Kirsten Emilie Moselund
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Patent number: 11735634Abstract: A method for forming heterogeneous complementary FETs using a compact stacked nanosheet process is disclosed. The method comprises forming a first nanosheet stack comprising two layers of a first channel material separated by a second sacrificial layer, forming over the first nanosheet stack an equivalent second nanosheet stack, wherein the first channel material is complementary to the second channel material. The method comprises further forming a first source region and a first drain region, thereby building a first FET, and forming over the first source region and the first drain region a second source region and a second drain region, thereby building a second FET, removing selectively sacrificial layers, and forming a gate stack comprising a gate-all-around structure around all channels.Type: GrantFiled: March 17, 2021Date of Patent: August 22, 2023Assignee: International Business Machines CorporationInventors: Cezar Bogdan Zota, Clarissa Convertino, Kirsten Emilie Moselund
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Publication number: 20230197842Abstract: One or more systems, devices, methods of use and/or methods of fabrication provided herein relate to a high-electron-mobility transistor with a gate electrode below the channel.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Inventors: Cezar Bogdan Zota, Eunjung Cha, Thomas Morf, Peter Mueller
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Patent number: 11683938Abstract: A magnetic field controlled transistor circuit includes a first electrode, a second electrode, and a channel including a magneto-resistive material. The channel is arranged between the first and second electrodes and electrically coupled to the first and second electrodes. The transistor circuit further includes a third electrode, a fourth electrode, and a control layer including an electrically conductive material. The control layer is arranged between the third and fourth electrodes and electrically coupled to the third and fourth electrodes. In addition, an insulating layer including an insulating material is provided. The insulating layer is arranged between the channel and the control layer and configured to electrically insulate the channel from the control layer. A related method for operating a transistor circuit and a corresponding design structure are also provided.Type: GrantFiled: December 30, 2020Date of Patent: June 20, 2023Assignee: International Business Machines CorporationInventors: Cezar Bogdan Zota, Bernd W. Gotsmann
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Publication number: 20230178642Abstract: A superconductor transistor structure includes a source electrode and a drain electrode on a same plane as the source electrode. There is a channel region on top of the source and drain electrodes and configured to carry a current. A gate structure comprising a metallic material is on top of the channel region. The source and drain are located on a side that is opposite to that of the gate structure, with respect to the channel region.Type: ApplicationFiled: December 5, 2021Publication date: June 8, 2023Inventors: Cezar Bogdan Zota, Thomas Morf, Eunjung Cha, Peter Mueller
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Publication number: 20230178641Abstract: A transistor structure, includes a buffer layer and a quantum well channel layer on top of the buffer layer. There is a barrier layer on top of the channel layer. There is a drain contact on a channel stack. A source contact is on a channel stack. A gate structure is located between the source contact and drain contact, comprising: an active gate portion having a bottom surface in contact with a bottom surface of the source and the drain contacts. A superconducting portion of the gate structure is in contact with, and adjacent to, an upper part of the active gate portion.Type: ApplicationFiled: December 3, 2021Publication date: June 8, 2023Inventors: Eunjung Cha, Cezar Bogdan Zota
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Publication number: 20230139805Abstract: The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.Type: ApplicationFiled: November 4, 2021Publication date: May 4, 2023Inventors: Thomas Morf, Cezar Bogdan Zota, Peter Mueller, Pier Andrea Francese, Marcel A. Kossel, Matthias Braendli, Mridula Prathapan
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Patent number: 11621340Abstract: The present disclosure relates to a method for fabricating a field-effect transistor structure on a substrate. The method includes forming a first semiconductor structure on the substrate, forming above the first semiconductor structure a gate structure that comprises a spacer layer laterally terminating the gate structure and has a lower etch rate than the first semiconductor structure with respect to a predetermined etchant, forming an undercut below the spacer layer by recessing the first semiconductor structure using the etchant, the undercut extending laterally below the spacer layer by not more than the thickness of the spacer layer, forming on the first semiconductor structure a second semiconductor structure filling the undercut, and forming a third semiconductor structure above the first semiconductor structure, wherein one of the second and third semiconductor structures forms the source of the field-effect transistor structure and the other one forms the drain.Type: GrantFiled: November 12, 2019Date of Patent: April 4, 2023Assignee: International Business Machines CorporationInventors: Clarissa Convertino, Cezar Bogdan Zota, Lukas Czornomaz, Kirsten Emilie Moselund
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Publication number: 20230088757Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of epitaxial source/drain regions connected to the plurality of channel layers. The plurality of channel layers are connected to the plurality of epitaxial source/drain regions via a plurality of epitaxial extension regions. Respective pairs of adjacent channel layers of the plurality of channel layers are connected to a given one of the plurality of epitaxial source/drain regions via respective ones of the plurality of epitaxial extension regions.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Nicolas Loubet, Shogo Mochizuki, Kirsten Emilie Moselund, Cezar Bogdan Zota
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Publication number: 20220301942Abstract: A method forms heterogeneous complementary FETs and a related semiconductor structure. The method comprises forming a layered nanosheet stack comprising two layers of a first channel material alternating with two layers of a second channel material, depositing a dielectric layer on a top layer of the nanosheet stack, and forming a checkered mask material with at least a first and a second row above the dielectric material. The first and the second row are distanced from each other. The method removes the first channel material and the second channel material outside an area of the checkered mask material, resulting in the at least a first row of pillars and a second row of pillars of layered nanosheet stacks. The method selectively removes in each of the pillars of the first stripe the second channel material.Type: ApplicationFiled: March 17, 2021Publication date: September 22, 2022Inventors: Cezar Bogdan Zota, Clarissa Convertino, Kirsten Emilie Moselund
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Publication number: 20220302269Abstract: A method for forming heterogeneous complementary FETs using a compact stacked nanosheet process is disclosed. The method comprises forming a first nanosheet stack comprising two layers of a first channel material separated by a second sacrificial layer, forming over the first nanosheet stack an equivalent second nanosheet stack, wherein the first channel material is complementary to the second channel material. The method comprises further forming a first source region and a first drain region, thereby building a first FET, and forming over the first source region and the first drain region a second source region and a second drain region, thereby building a second FET, removing selectively sacrificial layers, and forming a gate stack comprising a gate-all-around structure around all channels.Type: ApplicationFiled: March 17, 2021Publication date: September 22, 2022Inventors: Cezar Bogdan Zota, Clarissa Convertino, Kirsten Emilie Moselund
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Patent number: 11270999Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.Type: GrantFiled: April 7, 2021Date of Patent: March 8, 2022Assignee: International Business Machines CorporationInventors: Cezar Bogdan Zota, Clarissa Convertino, Lukas Czornomaz, Siegfried Friedrich Karg
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Patent number: 11201246Abstract: The present disclosure relates to a method for fabricating an FET structure. The method includes forming on a substrate a first semiconductor structure and an insulator structure covering the first semiconductor structure with a first insulator layer, forming on the first insulator layer a sacrificial layer extending to a reference plane, forming a second insulator layer on the reference plane, forming a first cavity through the second insulator layer, the sacrificial layer and the first insulator layer, thus exposing a surface of the first semiconductor structure, filling the first cavity with a second semiconductor structure extending from the surface at least up to the first reference plane, forming a third semiconductor structure on the second semiconductor structure, selectively removing the sacrificial layer, thus forming a second cavity, and filling the second cavity with a gate structure.Type: GrantFiled: November 12, 2019Date of Patent: December 14, 2021Assignee: International Business Machines CorporationInventors: Clarissa Convertino, Cezar Bogdan Zota, Kirsten Emilie Moselund, Lukas Czornomaz, Davide Cutaia
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Patent number: 11183978Abstract: An amplifier, e.g., a low-noise amplifier, includes a field-effect transistor having a one-dimensional channel. This channel includes a semiconductor material for conducting electrons along a main direction of the channel. This direction is perpendicular to a cross-section of the channel. Dimensions of this cross-section are, together with the semiconductor material, such that the channel exhibits quantized conduction of electrons along its main direction. The amplifier further includes an electrical circuit that is configured to operate the transistor at a value of gate-to-source voltage bias corresponding to a peak value of a peak of a transconductance of the channel with respect to gate-to-source voltage bias values.Type: GrantFiled: June 6, 2019Date of Patent: November 23, 2021Assignee: International Business Machines CorporationInventors: Cezar Bogdan Zota, Lukas Czornomaz
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Publication number: 20210225845Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.Type: ApplicationFiled: April 7, 2021Publication date: July 22, 2021Inventors: Cezar Bogdan Zota, Clarissa Convertino, Lukas Czornomaz, Siegfried Friedrich Karg
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Publication number: 20210175234Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.Type: ApplicationFiled: December 5, 2019Publication date: June 10, 2021Inventors: Cezar Bogdan Zota, Clarissa Convertino, Lukas Czornomaz, Siegfried Friedrich Karg
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Patent number: 11031402Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.Type: GrantFiled: December 5, 2019Date of Patent: June 8, 2021Assignee: International Business Machines CorporationInventors: Cezar Bogdan Zota, Clarissa Convertino, Lukas Czornomaz, Siegfried Friedrich Karg
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Publication number: 20210143263Abstract: The present disclosure relates to a method for fabricating a field-effect transistor structure on a substrate. The method includes forming a first semiconductor structure on the substrate, forming above the first semiconductor structure a gate structure that comprises a spacer layer laterally terminating the gate structure and has a lower etch rate than the first semiconductor structure with respect to a predetermined etchant, forming an undercut below the spacer layer by recessing the first semiconductor structure using the etchant, the undercut extending laterally below the spacer layer by not more than the thickness of the spacer layer, forming on the first semiconductor structure a second semiconductor structure filling the undercut, and forming a third semiconductor structure above the first semiconductor structure, wherein one of the second and third semiconductor structures forms the source of the field-effect transistor structure and the other one forms the drain.Type: ApplicationFiled: November 12, 2019Publication date: May 13, 2021Inventors: Clarissa Convertino, Cezar Bogdan Zota, Lukas Czornomaz, Kirsten Emilie Moselund
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Publication number: 20210143282Abstract: The present disclosure relates to a method for fabricating an FET structure. The method includes forming on a substrate a first semiconductor structure and an insulator structure covering the first semiconductor structure with a first insulator layer, forming on the first insulator layer a sacrificial layer extending to a reference plane, forming a second insulator layer on the reference plane, forming a first cavity through the second insulator layer, the sacrificial layer and the first insulator layer, thus exposing a surface of the first semiconductor structure, filling the first cavity with a second semiconductor structure extending from the surface at least up to the first reference plane, forming a third semiconductor structure on the second semiconductor structure, selectively removing the sacrificial layer, thus forming a second cavity, and filling the second cavity with a gate structure.Type: ApplicationFiled: November 12, 2019Publication date: May 13, 2021Inventors: Clarissa Convertino, Cezar Bogdan Zota, Kirsten Emilie Moselund, Lukas Czornomaz, Davide Cutaia