Patents by Inventor CH CHEW
CH CHEW has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942369Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: GrantFiled: July 30, 2020Date of Patent: March 26, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh Krishnan, Sw Wei Wang, Ch Chew, How Kiat Liew, Fui Fui Tan
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Publication number: 20240006363Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: ApplicationFiled: September 13, 2023Publication date: January 4, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw WANG, CH CHEW, Eiji KUROSE, How Kiat LIEW
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Patent number: 11791297Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: GrantFiled: February 4, 2022Date of Patent: October 17, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw Wang, Ch Chew, Eiji Kurose, How Kiat Liew
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Publication number: 20220157756Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: ApplicationFiled: February 4, 2022Publication date: May 19, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw WANG, CH CHEW, Eiji KUROSE, How Kiat LIEW
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Patent number: 11244918Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: GrantFiled: August 17, 2017Date of Patent: February 8, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw Wang, CH Chew, Eiji Kurose, How Kiat Liew
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Publication number: 20200357697Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: ApplicationFiled: July 30, 2020Publication date: November 12, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh KRISHNAN, Sw Wei WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN
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Patent number: 10763173Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: GrantFiled: April 26, 2019Date of Patent: September 1, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh Krishnan, Sw Wei Wang, Ch Chew, How Kiat Liew, Fui Fui Tan
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Publication number: 20190252255Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: ApplicationFiled: April 26, 2019Publication date: August 15, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh KRISHNAN, Sw Wei WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN
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Patent number: 10319639Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: GrantFiled: August 17, 2017Date of Patent: June 11, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh Krishnan, Sw Wang, CH Chew, How Kiat Liew, Fui Fui Tan
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Publication number: 20190115275Abstract: Implementations of semiconductor packages may include: a substrate comprising a first side and a second side and a hole in the substrate. The hole extending from the first side to the second side of the substrate and positioned in a center of the substrate. The semiconductor packages may also include a bushing around the hole to the first side of the substrate. The semiconductor packages may also include a plurality of pin holders arranged and coupled on the substrate. The semiconductor package may also include a molding compound at least partially encapsulating the substrate, encapsulating a side surface of the bushing, and encapsulating a plurality of side surfaces of the plurality of pin holders.Type: ApplicationFiled: October 13, 2017Publication date: April 18, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, CH Chew, Yushuang YAO
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Publication number: 20190057947Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw WANG, CH CHEW, Eiji KUROSE, How Kiat LIEW
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Publication number: 20190057900Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh KRISHNAN, Sw WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN