Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

Abstract: FinFET devices, along with methods for fabricating such devices, are disclosed herein for facilitating device characterization. An exemplary FinFET device includes a fin having a first portion extending in a first direction and a second portion extending from the first portion in a second direction. The second direction is substantially perpendicular to the first direction. The first portion includes a first region doped with a first type dopant disposed between second regions doped with a second type dopant. The first type dopant is opposite the second type dopant. A source contact and a drain contact are coupled to the second regions of the first portion, and a body contact is coupled to the second portion. A gate is disposed over the first region of the first portion, and the second portion extends from the first region.

Abstract: FinFET devices, along with methods for fabricating such devices, are disclosed herein for facilitating device characterization. An exemplary FinFET device includes a fin having a first portion extending in a first direction and a second portion extending from the first portion in a second direction. The second direction is substantially perpendicular to the first direction. The first portion includes a first region doped with a first type dopant disposed between second regions doped with a second type dopant. The first type dopant is opposite the second type dopant. A source contact and a drain contact are coupled to the second regions of the first portion, and a body contact is coupled to the second portion. A gate is disposed over the first region of the first portion, and the second portion extends from the first region.

Abstract: A method and system is disclosed for providing access to the body of a FinFET device. In one embodiment, a FinFET device for characterization comprises an active fin comprising a source fin, a depletion fin, and a drain fin; a side fin extending from the depletion fin and coupled to a body contact for providing access for device characterization; and a gate electrode formed over the depletion fin and separated therefrom by a predetermined dielectric layer, wherein the gate electrode and the dielectric layer thereunder have a predetermined configuration to assure the source and drain fins are not shorted.

Abstract: A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

Abstract: A method for forming a semiconductor device provides for forming a gate region on top of a substrate. Gate sidewall liners are formed on opposed sides of the gate region, the sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate. Recessed spacers are formed on top of the sidewall liners. The sidewall liner underneath the spacers is pulled back from the edge of the respective spacer by a predetermined distance. The recessed spacers are formed by reducing the height of the originally formed spacer. The height of the spacers is lower than a height of the gate sidewall liner and the width of the horizontal part of the sidewall liner is shorter than the width of the spacer. The reduced spacer height reduces device channel stress.

Abstract: A method and system is disclosed for providing access to the body of a FinFET device. In one embodiment, a FinFET device for characterization comprises an active fin comprising a source fin, a depletion fin, and a drain fin; a side fin extending from the depletion fin and coupled to a body contact for providing access for device characterization; and a gate electrode formed over the depletion fin and separated therefrom by a predetermined dielectric layer, wherein the gate electrode and the dielectric layer thereunder have a predetermined configuration to assure the source and drain fins are not shorted.

Abstract: A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

Abstract: A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

Abstract: A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

Abstract: A method for forming a semiconductor device provides for forming a gate region on top of a substrate. Gate sidewall liners are formed on opposed sides of the gate region, the sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate. Recessed spacers are formed on top of the sidewall liners. The sidewall liner underneath the spacers is pulled back from the edge of the respective spacer by a predetermined distance. The recessed spacers are formed by reducing the height of the originally formed spacer. The height of the spacers is lower than a height of the gate sidewall liner and the width of the horizontal part of the sidewall liner is shorter than the width of the spacer. The reduced spacer height reduces device channel stress.

Abstract: An integrated circuit having small layout area and a method of forming the same are provided. A slant contact is formed by shifting a portion of a contact a distance less than a whole dimension of the contact along the direction shifted. By using slant contacts, the optical proximity effect is reduced, the device density in the integrated circuit is increased and cross talk is reduced. In the preferred embodiment, the slant contact is combined with other techniques such as compound interconnection, butted local interconnection and slim spacers to reduce the layout area. In another embodiments, a six-transistor SRAM cell can be designed with a slant contact, compound interconnection and butted local interconnection to reduce the layout area.

Abstract: A semiconductor device includes a substrate and a gate region on top of a substrate. First and second gate sidewall liners are situated on first and second sides of the gate region respectively, the first and second sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate. First and second recessed spacers are situated on top of the first and second sidewall liners respectively. The height of the first and second spacers is lower than the height of the gate sidewall liner whereas the width of the horizontal part of the sidewall liner is shorter than the width of the spacer.

Abstract: A semiconductor device and the method for making same is disclosed. The semiconductor device has a substrate and a gate region on top of the substrate. It further has a first and second gate sidewall liners situated on a first and second sides of the gate region respectively, the first and second sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate; and a first and second recessed spacers situated on top of the first and second sidewall liners respectively, wherein a height of the first and second spacers is lower than a height of the gate sidewall liner and wherein the width of the horizontal part of the sidewall liner is shorter than the width of the spacer.

Abstract: An improved cutting apparatus for horticultural use comprises a first cutting device, a second cutting device, and a retaining plate. The second cutting device has a plurality of second elongated holes disposed thereon serving as sliding rails on which rolling beads travel. The retaining plate comprises a plurality of through holes through which rolling beads are partially exposed. The retaining plate also comprises a plurality of elastic press pieces affixed thereto, with each of elastic press pieces having a press portion located at one end thereof for pressing the exposed portion of the rolling beads so as to ensure that first and second cutting devices make a reciprocating motion in a linear manner.