Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.

Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.

Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.

Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.

Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.

Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.

Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.

Abstract: A finFET device and a method of forming are provided. The method includes forming a first dielectric layer over a transistor. The method also includes forming a second dielectric layer over the first dielectric layer. The method also includes forming a first opening in the second dielectric layer to expose at least a portion of a gate electrode of the transistor. The method also includes forming a second opening in the first dielectric layer to expose at least a portion of a source/drain region of the transistor. The second opening is connected to the first opening, and the first opening is formed before the second opening. The method also includes forming an electrical connector in the first opening and the second opening.

Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.

Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.

Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.

Abstract: A method for maintaining a smooth surface of crystallizable material is disclosed. First, a substrate is provided. A target material layer is then formed on the substrate, with the target material being a crystallizable material. A protecting layer is subsequently formed on the target material layer. Next, an annealing treatment is implemented, with the surface of the target material layer, facing the protecting layer, being maintained in its original smooth state by the pressure and/or adhesion of the protecting layer. Finally, the protecting layer is removed to leave an open and smooth surface of the processed crystallizable material.

Abstract: A method for maintaining a smooth surface of crystallizable material is disclosed. First, a substrate is provided. A target material layer is then formed on the substrate, with the target material being a crystallizable material. A protecting layer is subsequently formed on the target material layer. Next, an annealing treatment is implemented, with the surface of the target material layer, facing the protecting layer, being maintained in its original smooth state by the pressure and/or adhesion of the protecting layer. Finally, the protecting layer is removed to leave an open and smooth surface of the processed crystallizable material.

Abstract: The present invention discloses a high-efficiency lighting device and a method for fabricating the same. The method of the present invention comprises steps: providing an insulation substrate and sequentially forming an electrode layer and a seed layer on the insulation layer; forming a plurality of zinc oxide micro and nano structures and a plurality of first insulation units on the seed layer, wherein each zinc oxide micro and nano structure is arranged between two neighboring first insulation units; forming a nitride layer on the side wall of each zinc oxide micro and nano structure; and forming an electrode layer on each nitride layer. The present invention achieves a high-efficiency lighting device via growing nitride layers on the side walls of zinc oxide micro and nano structures. Further, the present invention can reduce the fabrication cost.

Abstract: The present invention discloses a high-efficiency lighting device and a method for fabricating the same. The method of the present invention comprises steps: providing an insulation substrate and sequentially forming an electrode layer and a seed layer on the insulation layer; forming a plurality of zinc oxide micro and nano structures and a plurality of first insulation units on the seed layer, wherein each zinc oxide micro and nano structure is arranged between two neighboring first insulation units; forming a nitride layer on the side wall of each zinc oxide micro and nano structure; and forming an electrode layer on each nitride layer. The present invention achieves a high-efficiency lighting device via growing nitride layers on the side walls of zinc oxide micro and nano structures. Further, the present invention can reduce the fabrication cost.

Abstract: A metallic photonic box capable of intensifying light at a certain wavelength, includes: a metallic surrounding forming a resonance chamber; and an insulator layer, disposed in the resonance chamber, having a predetermined dimension defining a cut-off wavelength, which inhibits light of a wavelength greater than the cut-off wavelength from resonating, whereby when the metallic photonic box is heated to generate light radiation, the light radiation is intensified at a wavelength rage predetermined by the cut-off wavelength.

Abstract: A metallic photonic box capable of intensifying light at a certain wavelength, includes: a metallic surrounding forming a resonance chamber; and an insulator layer, disposed in the resonance chamber, having a predetermined dimension defining a cut-off wavelength, which inhibits light of a wavelength greater than the cut-off wavelength from resonating, whereby when the metallic photonic box is heated to generate light radiation, the light radiation is intensified at a wavelength rage predetermined by the cut-off wavelength.