Abstract: A semiconductor package comprising: a substrate including an external connection terminal and a cavity; a first semiconductor chip disposed in the cavity, the first semiconductor chip including a first pad and a second pad different from the first pad, the first pad and the second pad being disposed on a first surface of the first semiconductor chip; a metal line disposed on the substrate and the first semiconductor chip and electrically connecting the first pad of the first semiconductor chip with the external connection terminal of the substrate; a second semiconductor chip disposed on the first semiconductor chip, the second semiconductor chip including a third pad disposed on a second surface of the second semiconductor chip facing the first semiconductor chip; and a connection terminal electrically connecting the second pad of the first semiconductor chip with the third pad of the second semiconductor chip, the connection terminal being not electrically connected to the metal line.

Abstract: A semiconductor package comprising: a substrate including an external connection terminal and a cavity; a first semiconductor chip disposed in the cavity, the first semiconductor chip including a first pad and a second pad different from the first pad, the first pad and the second pad being disposed on a first surface of the first semiconductor chip; a metal line disposed on the substrate and the first semiconductor chip and electrically connecting the first pad of the first semiconductor chip with the external connection terminal of the substrate; a second semiconductor chip disposed on the first semiconductor chip, the second semiconductor chip including a third pad disposed on a second surface of the second semiconductor chip facing the first semiconductor chip; and a connection terminal electrically connecting the second pad of the first semiconductor chip with the third pad of the second semiconductor chip, the connection terminal being not electrically connected to the metal line.

Abstract: A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove.

Abstract: A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove.

Abstract: In a semiconductor device stack package and a method of forming the same, the package comprises: a substrate; a plurality of lower chips stacked on the substrate and having an active surface oriented in a direction toward the substrate; and at least one upper chip disposed on the lower chips and connected to the substrate via a bump disposed between the lower chips. As no wire loops are formed, there is no increase in the height of the stack package, and the electrical path is shortened, thereby improving the electric performance of the stack package. Also, the semiconductor device stack package has a flip chip structure, and thus a plurality of semiconductor chips can be stacked in various manners.