Abstract: Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.

Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor of a semiconductor device having an upper and lower electrode formed of metal is provided. Portions of a conductive layer for a lower electrode on inner walls of holes are not removed. Portions of the conductive layer for a lower electrode outside the holes are selectively etched back and node-separated.

Abstract: Methods and apparatus for plasma annealing layers of a microelectronic capacitor on a substrate are provided to improve the leakage current characteristics of a capacitor and/or to reduce the number of impurities in an electrode.

Abstract: An integrated circuit device is formed by providing a substrate and forming a capacitor on the substrate. The capacitor includes a lower electrode disposed on the substrate, a dielectric layer on the lower electrode, and an upper electrode on the dielectric. A hydrogen barrier insulation layer is formed on the upper electrode and a hydrogen barrier spacer is formed on a sidewall of the capacitor.

Abstract: A ruthenium (Ru) film is formed on a substrate as part of a two-stage methodology. During the first stage, the Ru film is formed on the substrate in a manner in which the Ru nucleation rate is greater than the Ru growth rate. During the second stage, the Ru film is formed on the substrate in a manner in which the Ru growth rate is greater than the Ru nucleation rate.

Abstract: In a method of manufacturing a capacitor by performing a multi-stepped wet treatment on the surface of a metal electrode, a lower metal electrode of a capacitor is formed, and a primary wet treatment is performed on the surface of the lower metal electrode to remove unwanted surface oxides that may exist on the surface of the lower metal electrode. A secondary wet treatment is then performed on the surface of the lower metal electrode by using a different etchant than the etchant used in the primary wet treatment, in order to remove unwanted surface organic materials that may exist on the surface of the lower metal electrode. A dielectric layer is then formed on the lower metal electrode using a high-k dielectric material. An upper metal electrode is formed on the dielectric layer.

Abstract: Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium film includes supplying bis(isoheptane-2,4-dionato)norbornadiene ruthenium at a flow rate of 0.2-1 ccm and oxygen at a flow rate of 20-60 sccm, and depositing the ruthenium film at a temperature of 330-430° C. under a pressure of 0.5-5 Torr using chemical vapor deposition (CVD).

Abstract: Methods are provided for manufacturing an integrated circuit device in which a metal layer is formed on an integrated circuit substrate. A capping layer is formed on the metal layer opposite the integrated circuit substrate. The metal layer covered with the capping layer is heat-treated. The capping layer is removed and the metal layer, which is exposed by removal of the capping layer, is plasma-treated.

Abstract: A ruthenium (Ru) film is formed on a substrate as part of a two-stage methodology. During the first stage, the Ru film is formed on the substrate in a manner in which the Ru nucleation rate is greater than the Ru growth rate. During the second stage, the Ru film is formed on the substrate in a manner in which the Ru growth rate is greater than the Ru nucleation rate.

Abstract: A lower electrode is formed from a first metal on a semiconductor substrate. Atoms of a second metal, that is different than the first metal, are diffused into the lower electrode. A dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer. Diffusion of second metal atoms into the lower electrode may reduce or prevent crystal grain growth and agglomeration on a surface of the lower electrode during a subsequent high temperature process.

Abstract: Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.

Abstract: A method of manufacturing a semiconductor device having a metal layer is provided in which variation of surface morphology resulting from thermal oxidation is suppressed. The metal layer is pretreated at a first temperature so that an upper surface of the metal layer is changed into a mixed phase of metal and oxygen and becomes substantially resistant to further oxidation during a subsequent heating at a higher temperature in an oxygen atmosphere.

Abstract: A lower electrode is formed from a first metal on a semiconductor substrate. Atoms of a second metal, that is different than the first metal, are diffused into the lower electrode. A dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer. Diffusion of second metal atoms into the lower electrode may reduce or prevent crystal grain growth and agglomeration on a surface of the lower electrode during a subsequent high temperature process.

Abstract: Integrated circuit capacitors are provided having an electrically insulating electrode support layer having an opening therein on an integrated circuit substrate. A U-shaped lower electrode is provided in the opening and a first capacitor dielectric layer extends on an inner surface and an outer portion of the U-shaped lower electrode. A second capacitor dielectric layer extends between the outer portion of the U-shaped lower electrode and the first capacitor dielectric and also extends between the outer portion of the U-shaped lower electrode and an inner sidewall of the opening. An upper electrode extends on the first dielectric layer.

Abstract: A method for fabricating a semiconductor device is provided. The method includes the steps of: forming an insulating layer having an opening region on a semiconductor substrate; forming a first ruthenium layer on the insulating layer and the opening region by sputtering at a first pressure; forming a second ruthenium layer on the first ruthenium layer by first chemical vapor deposition (CVD) at a first flow rate of oxygen gas and at a second pressure, wherein the second pressure is greater than the first pressure; and forming a third ruthenium layer on the second ruthenium layer by second CVD at a second flow rate of oxygen gas and at a third pressure, wherein the third pressure is greater than the first pressure.

Abstract: A method of manufacturing a semiconductor device having a metal layer is provided in which variation of surface morphology resulting from thermal oxidation is suppressed. The metal layer is pretreated at a first temperature so that an upper surface of the metal layer is changed into a mixed phase of metal and oxygen and becomes substantially resistant to further oxidation during a subsequent heating at a higher temperature in an oxygen atmosphere.

Abstract: A layer is formed by chemical vapor depositing a seeding layer of ruthenium oxide on a substrate at a chemical vapor deposition flow rate ratio of a ruthenium source to oxygen gas. A main layer of ruthenium is chemical vapor deposited on the seeding layer by increasing the chemical vapor deposition flow rate ratio of the ruthenium source to the oxygen gas.

Abstract: A fabrication method for forming a semiconductor device having a capacitor is provided. A capacitor dielectric layer is formed by depositing a first layer and a second layer. The second layer is a major portion of the capacitor dielectric layer. The first layer acts as a seed layer, while the second layer is expitaxially grown. The material of the second layer as deposited is partially crystal. Nuclear generation and crystal growth occur separately so that the crystalline characteristic of the capacitor dielectric layer and the capacitance characteristic of the capacitor are enhanced. Moreover, the capacitor dielectric layer is crystallized at a relatively low temperature or for a relatively short time, thereby reducing leakage current as well as reducing deformation in the lower electrode. Optionally, The material of the second layer as deposited is not partially crystal but amorphous.

Abstract: Integrated circuit capacitors and methods of fabricating integrated circuit capacitors, according to the present invention, provide an electrically insulating electrode support layer having an opening therein, on an integrated circuit substrate. A U-shaped lower electrode is provided in the opening and a first capacitor dielectric layer extends on an inner surface and an outer portion of the U-shaped lower electrode. A second capacitor dielectric layer extends between the outer portion of the U-shaped lower electrode and the first capacitor dielectric and also extends between the outer portion of the U-shaped lower electrode and an inner sidewall of the opening. An upper electrode extends on the first dielectric layer.

Abstract: A dielectric region for a device such as a memory cell capacitor is formed by depositing a metal oxide, such as tantalum oxide, on a substrate at a first deposition rate in a first atmosphere maintained within a first temperature range and a first pressure range that produce a first tantalum oxide layer with a desirable step coverage. Metal oxide is subsequently deposited on the first metal oxide layer in a second atmosphere maintained within a second temperature range and a second pressure range that produce a second deposition rate greater than the first deposition rate to form a second tantalum oxide layer on the first tantalum oxide layer. For example, the first atmosphere may be maintained at a temperature in a range from about 350° C. to about 460° C. and a pressure in a range from about 0.01 Torr to about 2.0 Torr during formation of a first tantalum oxide layer, and the second atmosphere may be maintained at a temperature in a range from about 400° C. to about 500° C.