Abstract: Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a data server environment based at least in part on host managed hotness data. For example, a memory controller includes logic to receive a plurality of read and write requests from a host, where the plurality of read and write requests include an associated hotness data. A valid unit count of operational memory cells is maintained on a block-by-block basis for a plurality of memory blocks. A hotness index count is also maintained based at least in part on the hotness data on a block-by-block basis for the plurality of memory blocks. One or more memory blocks of the plurality of memory blocks are selected for eviction from a single level cell region to an x-level cell region based at least in part on the valid unit count and the hotness index count.

Abstract: Prefetch (e.g., prefetcher) circuits and methods that allow the safe prefetch of any speculative memory references using cryptographic addressing are described. In certain examples, a computing system includes a memory; a register to store a cryptographic address prefetch key; a core to generate a memory access request for the memory; a cache; and a prefetch circuit to: generate a speculative memory access request for an encrypted memory address based at least in part on the memory access request, decrypt the encrypted memory address to determine a memory line stored at the memory address decrypted by the cryptographic address prefetch key to generate a plaintext address, and store a memory line referenced by the plaintext address in the cache.

Abstract: Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a data server environment based at least in part on host managed hotness data. For example, a memory controller includes logic to receive a plurality of read and write requests from a host, where the plurality of read and write requests include an associated hotness data. A valid unit count of operational memory cells is maintained on a block-by-block basis for a plurality of memory blocks. A hotness index count is also maintained based at least in part on the hotness data on a block-by-block basis for the plurality of memory blocks. One or more memory blocks of the plurality of memory blocks are selected for eviction from a single level cell region to an x-level cell region based at least in part on the valid unit count and the hotness index count.

Abstract: An embodiment of a semiconductor apparatus may include technology to determine workload-related information for a persistent storage media and a cache memory, and aggregate a bandwidth of the persistent storage media and the cache memory based on the determined workload information. Other embodiments are disclosed and claimed.

Abstract: Embodiments are directed towards apparatuses, methods, and systems associated with a storage reclamation manager that generates a command to reclaim storage locations to assist in management of a storage capacity of a primary storage device. In embodiments, the command is a trim command to inform the storage device of storage locations including invalid data. In embodiments, the command is generated during performance of operations associated with a write-back operation where a cache coupled with the processor stores a first portion of data and the primary storage device stores a corresponding second portion of data. In embodiments, the command is generated during or after a write-back operation of a third portion of data into the cache device. In embodiments, the command assists in reclamation of storage locations in which the second portion of data is stored, to assist in management of a storage capacity of the primary storage device. Additional embodiments may be described and claimed.

Abstract: Embodiments are directed towards apparatuses, methods, and systems associated with a storage reclamation manager that generates a command to reclaim storage locations to assist in management of a storage capacity of a primary storage device. In embodiments, the command is a trim command to inform the storage device of storage locations including invalid data. In embodiments, the command is generated during performance of operations associated with a write-back operation where a cache coupled with the processor stores a first portion of data and the primary storage device stores a corresponding second portion of data. In embodiments, the command is generated during or after a write-back operation of a third portion of data into the cache device. In embodiments, the command assists in reclamation of storage locations in which the second portion of data is stored, to assist in management of a storage capacity of the primary storage device. Additional embodiments may be described and claimed.

Abstract: An embodiment of a semiconductor apparatus may include technology to determine workload-related information for a persistent storage media and a cache memory, and aggregate a bandwidth of the persistent storage media and the cache memory based on the determined workload information. Other embodiments are disclosed and claimed.