Patents by Inventor Chad A. Lindhorst

Chad A. Lindhorst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9305195
    Abstract: RFID readers transmit a Quiet Technology (QT) command to RFID tags causing at least one of the tags to transition between a private profile and a public profile. When a tag is inventoried in the private profile, it replies to the reader with contents from its private memory. When a tag is inventoried in the public profile, it replies to the reader with contents from its public memory, where the contents of the public memory may be a subset and/or modified version of the private memory contents, or entirely different altogether. The tag's profile can be switched again by another QT command from the reader, or following a loss of power at the tag. An access password and/or a short-range mechanism may be employed to allow only authorized readers to transition tag profiles or interrogate the private memory contents of tags in the public profile.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: April 5, 2016
    Assignee: IMPINJ, INC.
    Inventors: Christopher J. Diorio, Theron Stanford, Scott A. Cooper, Harley K. Heinrich, Chad A. Lindhorst, Kambiz Rahimi
  • Patent number: 9024731
    Abstract: RFID readers transmit a Quiet Technology (QT) command to RFID tags causing at least one of the tags to transition between a private profile and a public profile. When a tag is inventoried in the private profile, it replies to the reader with contents from its private memory. When a tag is inventoried in the public profile, it replies to the reader with contents from its public memory, where the contents of the public memory may be a subset and/or modified version of the private memory contents, or entirely different altogether. The tag's profile can be switched again by another QT command from the reader, or following a loss of power at the tag. An access password and/or a short-range mechanism may be employed to allow only authorized readers to transition tag profiles or interrogate the private memory contents of tags in the public profile.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 5, 2015
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Theron Stanford, Scott A. Cooper, Harley K. Heinrich, Chad A. Lindhorst, Kambiz Rahimi
  • Patent number: 8898425
    Abstract: Memory management units (MMUs) are disclosed. In one aspect, an MMU may have a first interface to a component. The first interface may receive one of a read of updated data from, and a write of updated data to, a virtual memory address. The virtual memory address may initially correspond to a first physical memory location in an only one time programmable (OTP) non-volatile memory (NVM). The MMU may have a remapping unit to remap a correspondence of the virtual memory address from the first physical memory location to a spare physical memory location. The MMU may also have a second interface to the OTP.NVM. The second interface may allow the updated data to be read from or written to the spare physical memory location of the OTP NVM. Methods performed by the MMUs, and methods and articles useful for manufacturing MMUs, are also disclosed.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: November 25, 2014
    Assignee: Synopsys, Inc.
    Inventors: Seth Pollack, Chad A. Lindhorst
  • Patent number: 8665074
    Abstract: RFID tags, ICs for RFID tags, and methods are provided. In some embodiments, an RFID tag includes a memory with multiple sections, and a processing block. The processing block may map one of these sections, or another of these sections, for purposes of responding to a first command from an RFID reader. As such, an RFID tag can operate according to the data stored in the section mapped at the time. In some embodiments, a tag can even transition from mapping one of the sections to mapping another of the sections. This can amount to the tag exhibiting alternative behaviors, and permits hiding data on the tag.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: March 4, 2014
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Theron Stanford, Scott A. Cooper, Chad A. Lindhorst, Kambiz Rahimi, Harley K. Heinrich, Gregory T. Kavounas
  • Patent number: 8471708
    Abstract: RFID readers transmit a Quiet Technology (QT) command to RFID tags causing at least one of the tags to transition between a private profile and a public profile. When a tag is inventoried in the private profile, it replies to the reader with contents from its private memory. When a tag is inventoried in the public profile, it replies to the reader with contents from its public memory, where the contents of the public memory may be a subset and/or modified version of the private memory contents, or entirely different altogether. The tag's profile can be switched again by another QT command from the reader, or following a loss of power at the tag. An access password and/or a short-range mechanism may be employed to allow only authorized readers to transition tag profiles or interrogate the private memory contents of tags in the public profile.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: June 25, 2013
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Theron Stanford, Scott A. Cooper, Harley K. Heinrich, Chad A. Lindhorst, Kambiz Rahimi
  • Patent number: 8433879
    Abstract: Memory management units (MMUs) are disclosed. In one aspect, an MMU may have a first interface to a component. The first interface may receive one of a read of updated data from, and a write of updated data to, a virtual memory address. The virtual memory address may initially correspond to a first physical memory location in an only one time programmable (OTP) non-volatile memory (NVM). The MMU may have a remapping unit to remap a correspondence of the virtual memory address from the first physical memory location to a spare physical memory location. The MMU may also have a second interface to the OTP NVM. The second interface may allow the updated data to be read from or written to the spare physical memory location of the OTP NVM. Methods performed by the MMUs, and methods and articles useful for manufacturing MMUs, are also disclosed.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: April 30, 2013
    Assignee: Synopsys, Inc.
    Inventors: Seth Pollack, Chad A. Lindhorst
  • Patent number: 8429375
    Abstract: Memory management units (MMUs) are disclosed. In one aspect, an MMU may have a first interface to a component. The first interface may receive one of a read of updated data from, and a write of updated data to, a virtual memory address. The virtual memory address may initially correspond to a first physical memory location in an only one time programmable (OTP) non-volatile memory (NVM). The MMU may have a remapping unit to remap a correspondence of the virtual memory address from the first physical memory location to a spare physical memory location. The MMU may also have a second interface to the OTP NVM. The second interface may allow the updated data to be read from or written to the spare physical memory location of the OTP NVM. Methods performed by the MMUs, and methods and articles useful for manufacturing MMUs, are also disclosed.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: April 23, 2013
    Assignee: Synopsys, Inc.
    Inventors: Seth Pollack, Chad A. Lindhorst
  • Patent number: 8279045
    Abstract: RFID tags and chips for RFID tags are capable of being inventoried in one or more early attempts. These tags are capable of then refraining from participating in one or more subsequent inventorying attempts. In some embodiments refraining is performed solely by the tag, while in others it is guided by the RFID reader. In some embodiments, an inventoried indicator in the tag becomes updated upon backscattering. The updated value is used by the tag to recognize a subsequent attempt, and thus refrain from participating in it. This permits the subsequent attempt to be used more intensively for inventorying the more elusive, harder-to-read tags, especially in more demanding scenarios.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: October 2, 2012
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Paul Dietrich, Theron Stanford, Chad Lindhorst, Kambiz Rahimi, Ali Aiouaz, Aanand Esterberg
  • Patent number: 8228175
    Abstract: RFID tags, ICs for RFID tags, and methods are provided. In some embodiments, an RFID tag includes a memory with multiple sections, and a processing block. The processing block may map one of these sections, or another of these sections, for purposes of responding to a first command from an RFID reader. As such, an RFID tag can operate according to the data stored in the section mapped at the time. In some embodiments, a tag can even transition from mapping one of the sections to mapping another of the sections. This can amount to the tag exhibiting alternative behaviors, and permits hiding data on the tag.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: July 24, 2012
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Theron Stanford, Scott A. Cooper, Chad A. Lindhorst, Kambiz Rahimi, Harley K. Heinrich, Gregory T. Kavounas
  • Patent number: 8122307
    Abstract: One Time Programmable (OTP) memory structures and methods for pretesting the support circuitry are provided. A group of dedicated test cells associated with one or more groups of regular OTP cells are used to test the support circuitry for the regular OTP cells. The dedicated cells are programmed and read. The read values are compared to the programmed values or expected values. As a result of the comparison, failing memories may be designated “Not Usable”, while regular OTP cells of passing memories can be programmed for their purpose resulting in elimination of wasted memories during test.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: February 21, 2012
    Assignee: Synopsys, Inc.
    Inventors: Chad A. Lindhorst, Todd E. Humes, Andrew E. Horch, Ernest Allen, III
  • Patent number: 8102007
    Abstract: A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: January 24, 2012
    Assignee: Synopsys, Inc.
    Inventors: John D. Hyde, Miguel E. Figueroa, Todd E. Humes, Christopher J. Diorio, Terry D. Hass, Chad A. Lindhorst
  • Patent number: 7724570
    Abstract: Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 25, 2010
    Assignee: Virage Logic Corporation
    Inventors: Chad A. Lindhorst, Todd E. Humes, Alex May, Agustinus Sutandi
  • Patent number: 7724571
    Abstract: Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 25, 2010
    Assignee: Virage Logic Corporation
    Inventors: Chad A. Lindhorst, Todd E. Humes, Alex May, Agustinus Sutandi
  • Patent number: 7573749
    Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: August 11, 2009
    Assignee: Virage Logic Corporation
    Inventors: Christopher J. Diorio, Chad A. Lindhorst, Shailendra Srinivas, Alberto Pesavento, Troy N. Gilliland
  • Publication number: 20080258916
    Abstract: RFID tags and chips for RFID tags are capable of being inventoried in one or more early attempts. These tags are capable of then refraining from participating in one or more subsequent inventorying attempts. In some embodiments refraining is performed solely by the tag, while in others it is guided by the RFID reader. In some embodiments, an inventoried indicator in the tag becomes updated upon backscattering. The updated value is used by the tag to recognize a subsequent attempt, and thus refrain from participating in it. This permits the subsequent attempt to be used more intensively for inventorying the more elusive, harder-to-read tags, especially in more demanding scenarios.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 23, 2008
    Applicant: Impinj, Inc.
    Inventors: Christopher J. Diorio, Paul Dietrich, Theron Stanford, Chad Lindhorst, Kambiz Rahimi, Ali Aiouaz, Aanand Esterberg
  • Publication number: 20080258878
    Abstract: RFID reader systems, readers, components, software and methods can inventory RFID tags in one or more early attempts. Then they can facilitate the inventoried RFID tags to refrain from participating in one or more subsequent inventorying attempts. In some embodiments, an inventoried indicator in the tag becomes updated upon backscattering. The updated value is used by the tag to recognize a subsequent attempt, and thus refrain from participating in it. This permits the subsequent attempt to be used more intensively for inventorying the more elusive, harder-to-read tags, especially in more demanding scenarios.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 23, 2008
    Applicant: Impinj, Inc.
    Inventors: Paul Dietrich, Christopher J. Diorio, Theron Stanford, Chad Lindhorst, Kambiz Rahimi, Ali Aiouaz, Aanand Esterberg
  • Publication number: 20070171724
    Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.
    Type: Application
    Filed: March 29, 2007
    Publication date: July 26, 2007
    Applicant: Impinj, Inc.
    Inventors: Christopher Diorio, Chad Lindhorst, Shailendra Srinivas, Alberto Pesavento, Troy Gilliland
  • Patent number: 7212446
    Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: May 1, 2007
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Chad A. Lindhorst, Shailendra Srinivas, Alberto Pesavento, Troy N. Gilliland
  • Patent number: 6950342
    Abstract: A number of designs for differential floating gate nonvolatile memories and memory arrays utilize differential pFET floating gate transistors to store information. Methods of implementing such memories and memory arrays together with methods of operation and test associated with such memories and memory arrays are presented.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: September 27, 2005
    Assignee: Impinj, Inc.
    Inventors: Chad A. Lindhorst, Christopher J. Diorio, Troy N. Gilliland, Alberto Pesavento, Shail Srinivas, Yanjun Ma, Terry Hass, Kambiz Rahimi
  • Publication number: 20050030827
    Abstract: A single-poly PMOS nonvolatile memory (NVM) cell and a method of programming, erasing and reading such a cell are implemented using a single-poly PMOS NVM cell which includes a floating gate injection transistor, a select switch, and a tunneling capacitor having one plate in common with the floating gate of the injection transistor. Methods of altering the number of electrons on the floating gate of the single-poly PMOS NVM cell are used which, with appropriate biasing of the components permit the power terminals of the cell to have appropriate voltages applied to thereby avoid stuck bits and induce hot electrons onto the floating gate of the NVM cell.
    Type: Application
    Filed: September 7, 2004
    Publication date: February 10, 2005
    Inventors: Troy Gilliland, Chad Lindhorst, Christopher Diorio, Todd Humes, Shailendra Srinivas