Abstract: An auction methodology wherein the auction competition among the bidders is generated by allowing each bidder to bid for non-price bid parameters (e.g., lead time, labor rate, contract length, etc.) in addition to the price of the lot on auction. Such a multi-parameter bidding provides the buyer (i.e., the auction requester) with more diverse information when selecting the winning bidder. The buyer and each bidder participating in the electronic auction may receive a real-time feedback of the bidding activity including details on bids placed for price and non-price parameters, which allows each bidder to adjust or modify one or more of its own bids (for price and non-price bid parameters) to effectively compete in the auction.

Abstract: Pneumatic particulate material fill systems and methods are disclosed. A particulate material fill system includes a cyclone separator having an inlet adapted to receive pneumatically conveyed particulate material. The cyclone separator has a first outlet adapted to vent air and a second outlet adapted to discharge solids. The particulate material fill system includes a tank adapted to receive solids discharged from the cyclone separator via the second outlet. The tank is adapted for use at atmospheric pressure.

Abstract: Pneumatic particulate material fill systems and methods are disclosed. A particulate material fill system includes a cyclone separator having an inlet adapted to receive pneumatically conveyed particulate material. The cyclone separator has a first outlet adapted to vent air and a second outlet adapted to discharge solids. The particulate material fill system includes a tank adapted to receive solids discharged from the cyclone separator via the second outlet. The tank is adapted for use at atmospheric pressure.

Abstract: A k-to-2k decoder is provided. Within the final stage of a k-to-2k decoder is a plurality of word line drivers. These word line drivers utilize clocking signals to fire word lines to a memory array. However, power consumption by clocks has become a serious issue with the increase component density on silicon wafers. To alleviate the problem, signals from the first stage of the k-to-2k decoder provide enablement signals to Local Clock Buffers (LCBs) that allow the word line drivers to fire. The enablement signal reduces the number of active buffers and signals carried to word line drivers, reducing power consumption.

Abstract: An assembly with a needle shield is provided. The needle shield includes a lock for preventing unwanted proximal and distal movement of the needle once the needle has been withdrawn into the needle shield.

Abstract: A medical needle assembly includes a needle cannula having a body and a tip. The tip is disposed at a distal end of the cannula. An elongate member has a first end and a second end. The first end is fixedly attached to the body of the needle cannula at a connection point and the second end extends radially outward from the needle body. A shield is slidingly mounted to the needle for movement between a proximal position to a distal position. The shield includes a shield body having a central chamber, a distal end and a proximal end as well as a plate secured to the shield body and defining an aperture. As the shield is moved from the proximal position to the distal position, the place displaces the second end of the elongate member to a position near the needle cannula, permitting the elongate member to pass through the aperture.

Abstract: An auction methodology wherein the auction competition among the bidders is generated by allowing each bidder to bid for non-price bid parameters (e.g., lead time, labor rate, contract length, etc.) in addition to the price of the lot on auction. Such a multi-parameter bidding provides the buyer (i.e., the auction requester) with more diverse information when selecting the winning bidder. The buyer and each bidder participating in the electronic auction may receive a real-time feedback of the bidding activity including details on bids placed for price and non-price parameters, which allows each bidder to adjust or modify one or more of its own bids (for price and non-price bid parameters) to effectively compete in the auction.

Abstract: A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.

Abstract: An apparatus, a method, and a computer program are provided to efficiently use a microprocessor array. Typically, microprocessor arrays can be divided into multiple subarrays. Also, in the conventional arrays, each of the subarrays were engaged when the microprocessor array is used. To alleviate the power consumed by the microprocessor arrays, row selection logic is employed to engage only specific rows of subarrays. Therefore, power consumed by unused subarrys is saved.

Abstract: An apparatus and methods for predicting and/or for calibrating memory yields due to process defects and/or device variations, including determining a model of a memory cell, identifying a subset of parameters associated with the model, determining and executing a refined model using the parameters, determining a predicted probability the simulated memory cell will be operational based on the simulated operation of the refined model, determining yield prediction information from the predicted probability, and determining the minimum number of repair elements to include in a memory array design to insure a desired yield percentage based on the yield prediction information.

Abstract: The invention proposes a Random Access Memory (1) with a plurality of symmetrical memory cells (2) which are connected in groups to complementary bit lines (blc, blt), and the complementary bit lines (blc, blt) are coupled through a cross coupled device (31, 32), and the groups of memory cells are connected to complementary global data lines (data_c, data_t) used to provide data to a selected cell of the group of memory cells. The Random Access Memory is characterized in that switches (33, 34) are provided that deactivate the cross coupled device, wherein the switches (33, 34) are driven by the complementary global data lines (data_c, data_t). The invention relates further on to a computer comprising such a Random Access Memory.

Abstract: A glitch protect valid cell and method for maintaining a desired logic state value in response to a glitch signal and a timing signal. The glitch protect valid cell may be integrated with a content addressable memory (CAM) array for indicating whether word data stored within the CAM is valid. The glitch protect valid cell includes a memory element, a state machine, and a glitch protect circuit each responsive to one another. The glitch protect circuit includes a propagation delay assembly and a restore assembly electrically coupled to one another. The propagation delay assembly includes a first pull down network and a NOR gate electrically coupled to one another. The restore assembly includes a second pull down network electrically coupled to the propagation delay assembly. The first pull down network is responsive to the glitch signal and the timing signal to selectively engage the NOR gate.

Abstract: In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.

Abstract: An assembly with a needle shield is provided. The needle shield includes a lock for preventing unwanted proximal and distal movement of the needle once the needle has been withdrawn into the needle shield.

Abstract: In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a first group of transistors adapted to store the bit and a second group of transistors adapted to affect a signal asserted during a read operation on a read bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the second group of transistors affects the signal asserted during the read operation on the read bit line coupled to the cell. Numerous other aspects are provided.

Abstract: An IV set may include a coupling for connecting the IV set to a source of liquid and a drip chamber including an access orifice, a top end having an inlet orifice, a bottom end having an outlet orifice, and a sidewall extending between the top end and the bottom end. The IV set may also include a valve connected to the access orifice for selectively controlling access to the drip chamber through the access orifice and a tube connected to the outlet orifice of the drip chamber. Additionally, the IV set may include a filter that permits air to flow through the filter while restricting the flow of liquid and an access port connected to the access orifice of the drip chamber.

Abstract: An IV set includes a drip chamber and a pressure activated valve. The drip chamber has an operable liquid height and an outlet orifice. The pressure activated valve is disposed proximate the outlet orifice of the drip chamber and includes a sealing orifice, a valve, and a biasing mechanism. The sealing orifice and the operable liquid height correspond to a head. The biasing mechanism biases the valve against the sealing orifice with a force less than the head of the operable liquid height to control the flow of liquid through the pressure activated valve.

Abstract: A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.

Abstract: A k-to-2k decoder is provided. Within the final stage of a k-to-2k decoder is a plurality of word line drivers. These word line drivers utilize clocking signals to fire word lines to a memory array. However, power consumption by clocks has become a serious issue with the increase component density on silicon wafers. To alleviate the problem, signals from the first stage of the k-to-2k decoder provide enablement signals to Local Clock Buffers (LCBs) that allow the word line drivers to fire. The enablement signal reduces the number of active buffers and signals carried to word line drivers, reducing power consumption.

Abstract: Data on a master is read into a master image file, and the master image file is manipulated to include a benchmark comprising tracking and verification information tied to at least a portion of the master image file. Thus, a copied-to storage media as copied from the master image file also includes such benchmark, a data alteration of the master image file causes a mis-match with regard to the benchmark in such master image file, and a data alteration of the copied-to storage media also causes a mis-match with regard to the benchmark in such storage media as copied from such master image file. The benchmark may include a part identifier and a security identifier.