Abstract: An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a current-mode logic differential amplifier and a common mode control circuit coupled to the current-mode logic differential amplifier. The common mode control circuit includes a replica circuit replicating a portion of the current-mode logic differential amplifier and a comparator circuit. The comparator circuit is configured to compare a voltage at a sense node in the replica circuit and a reference voltage and to provide to the current-mode logic differential amplifier and, via a feedback loop, to the replica circuit, an output that drives the sense node toward the reference voltage.

Abstract: Techniques for managing data flowing from mission critical systems. Embodiments include receiving a plurality of data values to transmit to a remote system using a unidirectional data communications network. The data values are prioritized according to a plurality of priority levels and the prioritized plurality of data values are grouped into one or more data updates for each of the plurality of priority levels. Embodiments enqueue the one or more data updates into a respective transmission queue corresponding to each of the plurality of priority levels and transmit the data updates over the unidirectional data communications network in an order determined based on the respective priority levels of the transmission queues.

Abstract: Described are systems and methods that enable secure real time communication (“RTC”) sessions that may be used, for example, for editing and movie production. Client devices may interact with an RTC management system to collaborate on different files retained on the different client devices, without the files having to be uploaded from the client device on which it is stored. In addition, on-going multifactor authentication may be performed for each client device of an RTC session during the RTC session and/or video authentication may be used to grant access into an RTC session. Still further, to improve the quality of the exchanged video information and to reduce transmission requirements, in response to detection of events, such as a pause event, a high resolution image of a paused video may be generated and sent for presentation on the display of each client device, instead of continuing to stream a paused video.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: A method is provided for providing an interface via an AR display for an operator to interact with displayed interactive graphical elements (IGEs) corresponding to respective actual components of a physical asset, wherein the interface is configured for the operator to control a selected actual component using a corresponding IGE, determining, responsive to detected user interaction with the corresponding IGE, whether the selected controllable actual component is designated as sensitive, and responsive to a determination that the selected controllable actual component is designated as sensitive, requiring enhanced multifactor authentication (MFA) to establish that the local user is local to the asset using a first factor of the enhanced MFA and that the local user is authenticated using a second factor of the enhanced MFA, and allowing control of the sensitive actual component based on receipt of proof of authentication of the local user by the enhanced MFA.

Abstract: Embodiments provide techniques for securely managing the transmission of register operations to endpoint devices (e.g., circuit breakers and other forms of electrical equipment). A firewall management component can add, through a secure communications channel, an entry to a firewall structure maintained on a firewall device. The entry can specify (i) a register operation for an endpoint device, (ii) a value for the register operation, and (iii) a count of times that the register operation can be performed. The firewall management component transmits register operation to the firewall device to be forwarded to the endpoint device. The firewall device is configured to forward the register operation to the endpoint device only if the count specified in the firewall structure would not be exceeded.

Abstract: Described are systems and methods that enable secure real time communication (“RTC”) sessions that may be used, for example, for editing and movie production. Client devices may interact with an RTC management system to obtain color calibration information so that the color presented on the different client devices is consistent with each other and corresponds to the intended color of the video for which collaboration is to be performed. In addition, on-going multifactor authentication may be performed for each client device of an RTC session during the RTC session. Still further, to improve the quality of the exchanged video information and to reduce transmission requirements, in response to detection of events, such as a pause event, a high resolution image of a paused video may be generated and sent for presentation on the display of each client device, instead of continuing to stream a paused video.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: Provided are embodiments for operating a high-speed deserializer. Embodiments can include receiving a clock slip signal to enable operation of the slip pulse generation circuit, and generating a slip pulse signal using the slip pulse-controlled clock generation circuit, wherein the slip pulse signal is programmable to slip one or more bits of a serial input data. Embodiments can also include generating a plurality of deserialization clocks for sampling the serial input data using the slip pulse-controlled clock generation circuit, wherein the plurality of deserialization clocks are generated simultaneously with each other, and providing the plurality of deserialization clocks to the deserializer to selectively sample the serial input data.

Abstract: Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.

Abstract: A high-speed voltage clamping circuit includes p-type field effect transistor (PFET) biasing circuit, an n-type field effect transistor (NFET) biasing circuit, and a field effect transistor (FET) clamp circuit. The PFET biasing circuit is configured to generate a PFET biasing voltage. The NFET biasing circuit is configured to generate a NFET biasing voltage. The FET clamp circuit is in signal communication with the PFET biasing circuit and the NFET biasing circuit. The PFET biasing circuit controls operation of the clamping circuit in response to a voltage overshoot event and the NFET biasing circuit controls operation of the clamping circuit in response to a voltage undershoot event.

Abstract: Provided are embodiments for operating a high-speed deserializer. Embodiments can include receiving a clock slip signal to enable operation of the slip pulse generation circuit, and generating a slip pulse signal using the slip pulse-controlled clock generation circuit, wherein the slip pulse signal is programmable to slip one or more bits of a serial input data. Embodiments can also include generating a plurality of deserialization clocks for sampling the serial input data using the slip pulse-controlled clock generation circuit, wherein the plurality of deserialization clocks are generated simultaneously with each other, and providing the plurality of deserialization clocks to the deserializer to selectively sample the serial input data.

Abstract: A high-speed voltage clamping circuit includes p-type field effect transistor (PFET) biasing circuit, an n-type field effect transistor (NFET) biasing circuit, and a field effect transistor (FET) clamp circuit. The PFET biasing circuit is configured to generate a PFET biasing voltage. The NFET biasing circuit is configured to generate a NFET biasing voltage. The FET clamp circuit is in signal communication with the PFET biasing circuit and the NFET biasing circuit. The PFET biasing circuit controls operation of the clamping circuit in response to a voltage overshoot event and the NFET biasing circuit controls operation of the clamping circuit in response to a voltage undershoot event.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: A method includes determining a phase error for a first clock signal and a second clock signal and determining an offset based on the phase error for the first clock signal and the second clock signal. The method also includes adding the offset to a phase of the first clock signal to produce a first adjusted clock signal and subtracting the offset from a phase of the second clock signal to produce a second adjusted clock signal. A phase error for the first adjusted clock signal and the second adjusted clock signal is smaller than the phase error for the first clock signal and the second clock signal.

Abstract: Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.

Abstract: A method includes connecting inputs of a first plurality of interpolation branches to a first clock signal, connecting inputs of a second plurality of interpolation branches to a second clock signal, and connecting inputs of a third plurality of interpolation branches to a third clock signal. The method also includes combining outputs of the first plurality of interpolation branches, the second plurality of interpolation branches, and the third plurality of interpolation branches to produce an output clock signal and adjusting a phase of the output clock signal by connecting an input of an interpolation branch of the third plurality of interpolation branches to the second clock signal.

Abstract: A method includes connecting inputs of a first plurality of interpolation branches to a first clock signal, connecting inputs of a second plurality of interpolation branches to a second clock signal, and connecting inputs of a third plurality of interpolation branches to a third clock signal. The method also includes combining outputs of the first plurality of interpolation branches, the second plurality of interpolation branches, and the third plurality of interpolation branches to produce an output clock signal and adjusting a phase of the output clock signal by connecting an input of an interpolation branch of the third plurality of interpolation branches to the second clock signal.

Abstract: Aspects of the invention include a driver arranged at a stand-alone receiver that is configured to receive a binary sequence from a pseudorandom binary sequence (PRBS) generator arranged at the receiver. The driver is configured to adjust the signal characteristics of the binary sequence to simulate channel loss at the receiver. The driver is further configured to output the adjusted binary sequence to a downstream data path of the receiver to enable the receiver to perform a self-test.