Patents by Inventor Chad B. McBride
Chad B. McBride has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9405315Abstract: A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.Type: GrantFiled: August 19, 2015Date of Patent: August 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark D. Bellows, Mark S. Fredrickson, Scott D. Frei, Steven P. Jones, Chad B. McBride
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Publication number: 20150355673Abstract: A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.Type: ApplicationFiled: August 19, 2015Publication date: December 10, 2015Inventors: Mark D. Bellows, Mark S. Fredrickson, Scott D. Frei, Steven P. Jones, Chad B. McBride
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Patent number: 9146835Abstract: A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.Type: GrantFiled: January 5, 2012Date of Patent: September 29, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark D. Bellows, Mark S. Fredrickson, Scott D. Frei, Steven P. Jones, Chad B. McBride
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Publication number: 20140195777Abstract: In a particular embodiment, a method may include creating a plurality of variable depth instruction FIFOs and a plurality of data caches from a plurality of caches corresponding to a plurality of processors, where the plurality of caches and the plurality of processors correspond to MIMD architecture. The method may also include configuring the plurality of variable depth instruction FIFOs to implement SIMD architecture. The method may also include configuring the plurality of variable depth instruction FIFOs for at least one of SIMD operation, SIMD operation with staging, or RC-SIMD operation.Type: ApplicationFiled: January 10, 2013Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark D. Bellows, Mark S. Fredrickson, Scott D. Frei, Steven P. Jones, Chad B. McBride
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Patent number: 8589630Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.Type: GrantFiled: July 3, 2012Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: John D. Irish, Chad B. McBride, Andrew H. Wottreng
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Publication number: 20130179720Abstract: A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.Type: ApplicationFiled: January 5, 2012Publication date: July 11, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark D. Bellows, Mark S. Fredrickson, Scott D. Frei, Steven P. Jones, Chad B. McBride
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Patent number: 8327075Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.Type: GrantFiled: December 8, 2005Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: John D. Irish, Chad B. McBride, Andrew H. Wottreng
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Publication number: 20120272009Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.Type: ApplicationFiled: July 3, 2012Publication date: October 25, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John D. Irish, Chad B. McBride, Andrew H. Wottreng
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Patent number: 8196074Abstract: An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.Type: GrantFiled: March 18, 2009Date of Patent: June 5, 2012Assignee: International Business Machines CorporationInventors: Mark S. Fredrickson, Glen Howard Handlogten, Chad B. McBride
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Patent number: 8127082Abstract: A method and apparatus for allowing multiple devices access to an address translation cache while cache maintenance operations are occurring at the same time. By interleaving the commands requiring address translation with maintenance operations that may normally take many cycles, address translation requests may have faster access to the address translation cache than if maintenance operations were allowed to stall commands requiring address translations until the maintenance operation was completed.Type: GrantFiled: February 1, 2006Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Chad B. McBride, Andrew H. Wottreng, John D. Irish
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Patent number: 7917700Abstract: A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a requirement for replacement in a congruence class is identified, a first PLRU cache line for replacement and an alternate PLRU cache line for replacement in the congruence class are calculated. When the first PLRU cache line for replacement is in the victim cache coherency state, the alternate PLRU cache line is picked for use.Type: GrantFiled: October 25, 2007Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventors: John David Irish, Chad B. McBride, Jack Chris Randolph
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Publication number: 20100188126Abstract: A method, system and apparatus for controlling the duty cycle of a clock to optimize duty cycle correction and non over-lapping clock generation. The first system generates a reference voltage and one or more clock signals. A comparison is made between the DC level of an output clock and the reference voltage. A correct duty cycle of the clock signal is equal to a predetermined ratio of high time to low time, within an acceptable margin, wherein the ratio of high time to low time is derived from a first resistor and a second resistor. A second system is developed to generate non-overlap clock signals with non-overlap gap control, wherein a reference voltage of a first circuit network is the reference voltage of a second circuit network; thereby generating a single reference signal for the non-overlap circuit network.Type: ApplicationFiled: January 26, 2009Publication date: July 29, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sharon W. Cheung, Chad B. McBride, Cheng-Fu Frank Tsai, Jianguo Yao
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Patent number: 7716423Abstract: The present invention provides an improved way to calculate a replacement way within a processor cache that is effective with different combinations of hardware address translation cache miss handling, software address translation cache miss handling, and hint lock bits. For some embodiments, LRU bits used to select an entry for replacement are updated only if software address translation cache miss handling is disabled. Further, for some embodiments, LRU bits may be modified to change the way a binary tree structure is traversed to avoid selecting a hint locked entry for replacement.Type: GrantFiled: February 7, 2006Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: John D. Irish, Chad B. McBride, Andrew H. Wottreng
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Patent number: 7634591Abstract: Methods and apparatus for tracking dependencies of commands to be executed by a command processor are provided. By determining the dependency of incoming commands against all commands awaiting execution, dependency information can be stored in a dependency scoreboard. Such a dependency scoreboard may be used to determine if a command is ready to be issued by the command processor. The dependency scoreboard can also be updated with information relating to the issuance of commands, for example, as commands complete.Type: GrantFiled: January 26, 2006Date of Patent: December 15, 2009Assignee: International Business Machines CorporationInventors: John David Irish, Chad B. McBride
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Publication number: 20090187695Abstract: Apparatus handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit to an address translation unit. When an address translation cache miss occurs, a memory fetch request is sent. The CBI is passed back to the command processing unit with a signal to indicate that the fetch request has completed. The command processing unit uses the CBI to locate the command and address to be reissued to the address translation unit.Type: ApplicationFiled: January 12, 2009Publication date: July 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John D. Irish, Chad B. McBride, Ibrahim A. Ouda, Andrew H. Wottreng
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Publication number: 20090178014Abstract: An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.Type: ApplicationFiled: March 18, 2009Publication date: July 9, 2009Applicant: International Business Machines CorporationInventors: Mark S. Fredrickson, Glen Howard Handlogten, Chad B. McBride
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Patent number: 7543204Abstract: Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each section including a gate receiving inputs of a global clock and a chain-specific clock control signal for a particular scan chain. A plurality of scan chains is defined, each including a plurality of latches. Each scan chain latch is connected to a corresponding chain-specific clock tree section.Type: GrantFiled: July 28, 2005Date of Patent: June 2, 2009Assignee: International Business Machines CorporationInventors: Mark S. Fredrickson, Glen Howard Handlogten, Steven Paul Jones, Chad B. McBride
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Patent number: 7539840Abstract: A method handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit to an address translation unit. When an address translation cache miss occurs, a memory fetch request is sent. The CBI is passed back to the command processing unit with a signal to indicate that the fetch request has completed. The command processing unit uses the CBI to locate the command and address to be reissued to the address translation unit.Type: GrantFiled: May 30, 2006Date of Patent: May 26, 2009Assignee: International Business Machines CorporationInventors: John D. Irish, Chad B. McBride, Ibrahim A. Ouda, Andrew H. Wottreng
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Publication number: 20090113134Abstract: A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a requirement for replacement in a congruence class is identified, a first PLRU cache line for replacement and an alternate PLRU cache line for replacement in the congruence class are calculated. When the first PLRU cache line for replacement is in the victim cache coherency state, the alternate PLRU cache line is picked for use.Type: ApplicationFiled: October 25, 2007Publication date: April 30, 2009Inventors: John David Irish, Chad B. McBride, Jack Chris Randolph
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Patent number: 7509611Abstract: An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.Type: GrantFiled: February 7, 2006Date of Patent: March 24, 2009Assignee: International Business Machines CorporationInventors: Mark S. Fredrickson, Glen Howard Handlogten, Chad B. McBride