Abstract: Based on a current activity running on a first selection of components operating in a primary mode from among redundant components within a high availability system, a separate power setting is selected for each separate type of redundant component from among the types of redundant components within the redundant components as specified in a high availability status specified for the current activity. At least one controller interface is called with a request to set the powered state of a particular component that is redundant to at least one of the first selection of components, from among a second selection of components operating in a standby mode from among the redundant components, to the separate power setting for the separate type of redundant component.

Abstract: Based on a current activity running on a first selection of components operating in a primary mode from among redundant components within a high availability system, a separate power setting is selected for each separate type of redundant component from among the types of redundant components within the redundant components as specified in a high availability status specified for the current activity. At least one controller interface is called with a request to set the powered state of a particular component that is redundant to at least one of the first selection of components, from among a second selection of components operating in a standby mode from among the redundant components, to the separate power setting for the separate type of redundant component.

Abstract: Based on a current activity running on a first selection of components operating in a primary mode from among redundant components within a high availability system, a separate power setting is selected for each separate type of redundant component from among the types of redundant components within the redundant components as specified in a high availability status specified for the current activity. At least one controller interface is called with a request to set the powered state of a particular component that is redundant to at least one of the first selection of components, from among a second selection of components operating in a standby mode from among the redundant components, to the separate power setting for the separate type of redundant component.

Abstract: Based on a current activity running on a first selection of components operating in a primary mode from among redundant components within a high availability system, a separate power setting is selected for each separate type of redundant component from among the types of redundant components within the redundant components as specified in a high availability status specified for the current activity. At least one controller interface is called with a request to set the powered state of a particular component that is redundant to at least one of the first selection of components, from among a second selection of components operating in a standby mode from among the redundant components, to the separate power setting for the separate type of redundant component.

Abstract: An approach for management of boot time of a virtual machine is provided. In one aspect, a system boot time application identifies assigned resources of a virtual I/O server (VIOS) of a computing system. In addition, the system boot time application allocates additional resources from client logical partitions (LPARs) of the computing system to the assigned resources of VIOS during boot time of VIOS. The system boot time application further identifies cores of the computing system during the boot time of VIOS. The system boot time application also sets the cores in turbo core mode until boot time of VIOS is completed. In one aspect, the system boot time application reallocates the allocated additional resources from VIOS to the client LPARs once boot time of VIOS is completed.

Abstract: An approach for management of boot time of a virtual machine is provided. In one aspect, a system boot time application identifies assigned resources of a virtual I/O server (VIOS) of a computing system. In addition, the system boot time application allocates additional resources from client logical partitions (LPARs) of the computing system to the assigned resources of VIOS during boot time of VIOS. The system boot time application further identifies cores of the computing system during the boot time of VIOS. The system boot time application also sets the cores in turbo core mode until boot time of VIOS is completed. In one aspect, the system boot time application reallocates the allocated additional resources from VIOS to the client LPARs once boot time of VIOS is completed.

Abstract: An approach for management of boot time of a virtual machine is provided. In one aspect, a system boot time application identifies assigned resources of a virtual I/O server (VIOS) of a computing system. In addition, the system boot time application allocates additional resources from client logical partitions (LPARs) of the computing system to the assigned resources of VIOS during boot time of VIOS. The system boot time application further identifies cores of the computing system during the boot time of VIOS. The system boot time application also sets the cores in turbo core mode until boot time of VIOS is completed. In one aspect, the system boot time application reallocates the allocated additional resources from VIOS to the client LPARs once boot time of VIOS is completed.

Abstract: An approach for management of boot time of a virtual machine is provided. In one aspect, a system boot time application identifies assigned resources of a virtual I/O server (VIOS) of a computing system. In addition, the system boot time application allocates additional resources from client logical partitions (LPARs) of the computing system to the assigned resources of VIOS during boot time of VIOS. The system boot time application further identifies cores of the computing system during the boot time of VIOS. The system boot time application also sets the cores in turbo core mode until boot time of VIOS is completed. In one aspect, the system boot time application reallocates the allocated additional resources from VIOS to the client LPARs once boot time of VIOS is completed.

Abstract: Mechanisms for adjusting direction of data flow between input/output (I/O) bridges and I/O hubs based on real time traffic levels are provided. The mechanisms of the illustrative embodiments provide firmware and/or hardware for monitoring data flow through an I/O bridge loop and corresponding I/O hub in order to determine if a condition exists requiring reassignment of the direction each I/O bridge sends its data. In particular, the firmware/hardware determines whether a current traffic condition through the I/O bridges and I/O hub meets criteria indicative of one pathway through the I/O bridge loop being over-utilized while another pathway through the I/O bridge loop is under-utilized. If it is determined that such a condition exists, the configuration of the I/O bridges may be automatically modified to reassign which pathway is utilized by the I/O bridge in sending/receiving I/O data traffic through the I/O bridge loop.

Abstract: Mechanisms for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.

Abstract: In a dynamic mode, firmware sets a threshold of errors that may occur within a predetermined period of time. If the threshold is exceeded, the firmware queries the front-side bus performance counters to determine whether the front-side bus is operating at its maximum data rate. If the front-side bus is not running at the maximum data rate, then the firmware bumps the data rate settings for the endpoint that exceeds the threshold by one step. If the front-side bus is running at its maximum data rate, then the firmware queries all the endpoints to determine which endpoints are active. The firmware then determines whether there are any active endpoints that are lower priority than the complaining endpoint. The mechanism drops the lower priority endpoints by one step and raises the complaining endpoint by one step.

Abstract: In a dynamic mode, firmware sets a threshold of errors that may occur within a predetermined period of time. If the threshold is exceeded, the firmware queries the front-side bus performance counters to determine whether the front-side bus is operating at its maximum data rate. If the front-side bus is not running at the maximum data rate, then the firmware bumps the data rate settings for the endpoint that exceeds the threshold by one step. If the front-side bus is running at its maximum data rate, then the firmware queries all the endpoints to determine which endpoints are active. The firmware then determines whether there are any active endpoints that are lower priority than the complaining endpoint. The mechanism drops the lower priority endpoints by one step and raises the complaining endpoint by one step.

Abstract: A system for reassigning root complex resources in a multi-root PCI express system identifies resources from a lower performing root complex port and reassigns those resources to the higher performing root complex. The system does not change the number of PCI Express lanes, the resources each root complex uses may be reassigned to allow those resources to be translated to available credits for an endpoint. For example, in one embodiment, two root complexes are configured as x8 root complexes with the root complex resources distributed across the two root complexes based upon the usage of the root complex resources.

Abstract: A system and method for adjusting direction of data flow between input/output (I/O) bridges and I/O hubs based on real time traffic levels are provided. The mechanisms of the illustrative embodiments provide firmware and/or hardware for monitoring data flow through an I/O bridge loop and corresponding I/O hub in order to determine if a condition exists requiring reassignment of the direction each I/O bridge sends its data. In particular, the firmware/hardware determines whether a current traffic condition through the I/O bridges and I/O hub meets criteria indicative of one pathway through the I/O bridge loop being over-utilized while another pathway through the I/O bridge loop is under-utilized. If it is determined that such a condition exists, the configuration of the I/O bridges may be automatically modified to reassign which pathway is utilized by the I/O bridge in sending/receiving I/O data traffic through the I/O bridge loop.

Abstract: A system and method for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.

Abstract: A multiple fan monitoring circuit for use with a plurality of fans, wherein each of the fans operates at a different frequency and generates a tach signal indicative of the fan operation, including a number of waveform shaping networks coupled to a corresponding one of the fans and utilized to waveshape a tach signal generated by its corresponding fan. The multiple fan monitoring circuit also includes a frequency processing circuit, coupled to the waveform shaping networks, that receives the waveshaped tach signals at a single sense node. The frequency processing circuit includes a summing circuit, coupled to the single sense node, that combines the waveshaped tach signals into a single combined signal, and a frequency discriminator, coupled to the summing circuit, that separates the single combined signal into multiple components, wherein each of the multiple components corresponds to a particular fan.

Abstract: A multiple fan monitoring circuit for use with a plurality of fans, wherein each of the fans operates at a different frequency and generates a tach signal indicative of the fan operation. The multiple fan monitoring circuit includes a number of waveform shaping networks, wherein each of the waveform shaping networks is coupled to a corresponding one of the fans. Each of the waveform shaping circuit is utilized to waveshape a tach signal generated by its corresponding fan. The multiple fan monitoring circuit also includes a frequency processing circuit, coupled to the waveform shaping networks, that receives the waveshaped tach signals at a single sense node. In a related embodiment, the frequency processing circuit includes a summing circuit, coupled to the single sense node, that combines the waveshaped tach signals into a single combined signal.