Abstract: Methods and apparatus for providing a bus interface are disclosed. An example bus interface includes a first power supply bus configured to distribute a first power supply voltage to first circuitry during a normal operating mode of the bus interface and power off during a low power operating mode of the bus interface. The example bus interface also includes a second power supply bus configured to distribute the first power supply voltage to second circuitry during the normal operating mode and distribute a second power supply voltage to the second circuitry during the low power operating mode. The example bus interface further includes a selection device coupled with the first power supply bus and the second power supply bus, where the selection device is configured to transition the bus interface between the normal operating mode and the low power operating mode in response to a received signal.

Abstract: Embodiments described herein relate to dividers and folders with tabs adjustable along at least two edges thereof. One embodiment is directed to a folder comprising a first panel, a second panel coupled to the first panel, at least one tab mating feature associated with the second panel, and a tab configured to mate with the at least one tab mating feature. The at least one tab mating feature is configured such that the tab is positionable in at least two positions along a first axis adjacent a first edge of the second panel and in at least two positions along a second axis adjacent a second edge of the second panel, wherein the first axis is transverse to the second axis.

Abstract: Methods and apparatus for providing a bus interface are disclosed. An example bus interface includes a first power supply bus configured to distribute a first power supply voltage to first circuitry during a normal operating mode of the bus interface and power off during a low power operating mode of the bus interface. The example bus interface also includes a second power supply bus configured to distribute the first power supply voltage to second circuitry during the normal operating mode and distribute a second power supply voltage to the second circuitry during the low power operating mode. The example bus interface further includes a selection device coupled with the first power supply bus and the second power supply bus, where the selection device is configured to transition the bus interface between the normal operating mode and the low power operating mode in response to a received signal.

Abstract: Methods and apparatus for providing a bus interface are disclosed. An example method for providing a bus interface includes operating first circuitry using a first power supply voltage in a normal operating mode, where the first circuitry includes at least a portion of datapath circuitry of the bus interface. The example method further includes powering down the first circuitry in a low power operating mode and operating second circuitry using the first power supply voltage in the normal operating mode. The example method also includes operating the second circuitry using a second power supply voltage in the low power operating mode. The second circuitry includes a power management control circuit adapted to receive a power management event indication signal. Responsive to the power management event indication signal, the control circuit provides at least one of an in-band power management indication and an out-of-band power management indication to one or more devices in a computing system.

Abstract: Embodiments described herein relate to dividers and folders with tabs adjustable along at least two edges thereof. One embodiment is directed to a folder comprising a first panel, a second panel coupled to the first panel, at least one tab mating feature associated with the second panel, and a tab configured to mate with the at least one tab mating feature. The at least one tab mating feature is configured such that the tab is positionable in at least two positions along a first axis adjacent a first edge of the second panel and in at least two positions along a second axis adjacent a second edge of the second panel, wherein the first axis is transverse to the second axis.

Abstract: The disclosed systems and methods relate to reducing the effect of video processing latency in devices that utilize PCI Express Active State Power Management (PCI-E ASPM). Power state transition delay may be reduced by initiating an early L1 exit based on a video processing stimulus. Aspects of the present invention may enable a higher level of performance and responsiveness while supporting the benefits of ASPM. Aspects of the present invention may be embodied in a video processing device that uses a video accelerator with a PCI-E interface.

Abstract: Methods and apparatus for providing a bus interface are disclosed. An example method for providing a bus interface includes operating first circuitry using a first power supply voltage in a normal operating mode, where the first circuitry includes at least a portion of datapath circuitry of the bus interface. The example method further includes powering down the first circuitry in a low power operating mode and operating second circuitry using the first power supply voltage in the normal operating mode. The example method also includes operating the second circuitry using a second power supply voltage in the low power operating mode. The second circuitry includes a power management control circuit adapted to receive a power management event indication signal. Responsive to the power management event indication signal, the control circuit provides at least one of an in-band power management indication and an out-of-band power management indication to one or more devices in a computing system.

Abstract: An instruction memory shared by a number of processing units has a plurality of individually accessible sections. A software program in the instruction memory is distributed among the memory sections. Sequential parts of the software program are in sequential sections. The software program may have a common portion which is repeated in each of the memory sections. Arbiter logic may control which of the processing units accesses which of the memory sections in each memory access cycle.

Abstract: Apparatus for transmitting a data stream between cards connected by a midplane breaks the data stream into a plurality of channels. The apparatus comprises a serializer for each channel. Serialized data is transmitted across the midplane to a deserializer at the destination. Sequential cells are sent in different channels. Cell ordering is preserved by staggering the start of cell transmission in the channels. The invention permits data to be transmitted across a mid plane using a reduced number of data lines. The data stream on each card may be carried in a wide bus at a relatively low clock rate. Apparatus according to the invention may be used to transmit an OC-192 data stream across a pin-limited interface.

Abstract: A packet processing device has an on-board match engine memory. Actions to be taken on a packet can be looked up in the match engine memory using a key comprising a match engine index and a protocol field from the packet. The match engine index is obtained from either a relatively small on-board parser memory or a larger context memory. The parser memory contains match engine indices for sparse protocols. Performance approaching that of hard-wired packet processors can be obtained. New protocols or changes in protocols can be accommodated by writing new values into the match engine, parser and context memories. The packet processing device can be provided in a pipelined architecture.