Patents by Inventor CHAD M. ALBERTSON
CHAD M. ALBERTSON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11776574Abstract: Techniques for authentication of digital recordings are provided. An element of encrypted data is output in a recording environment. The element of encrypted data, embedded in a digital recording comprising at least one of audio data and image data captured in the recording environment, is extracted. A decrypted value is generated based on a private key and the first element of encrypted data, and the first decrypted value and a stored value associated with a first element of the digital recording are compared. The digital recording is authenticated based on the first decrypted value substantially matching the stored value.Type: GrantFiled: December 21, 2020Date of Patent: October 3, 2023Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Mark S. Fredrickson, David G. Wheeler, Scott D. Frei
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Patent number: 10957355Abstract: Performing an operation comprising extracting a first element of encrypted data embedded in a digital recording comprising at least one of audio data and image data captured in a recording environment, generating a first decrypted value, the generating performed by execution of a cryptography algorithm based on a private key and the first element of encrypted data, comparing the first decrypted value and a stored value associated with a first element of the digital recording, and authenticating the digital recording based on the first decrypted value substantially matching the stored value.Type: GrantFiled: February 28, 2018Date of Patent: March 23, 2021Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Mark S. Fredrickson, David G. Wheeler, Scott D. Frei
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Patent number: 10927567Abstract: A lock system and method for alerting a user or other entity that a lock has been or is being tampered with is disclosed. The lock includes at least one enhanced security pin that is electrically isolated from the rest of the lock. When the lock picker attempts to pick the lock a portion of the enhanced security pin contacts either the plug or the outer casing of the lock to complete a circuit with an alert component. The completion of the circuit causes the alert component to generate an alert signal that can be observed by the user or other entity.Type: GrantFiled: January 1, 2019Date of Patent: February 23, 2021Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Patent number: 10796030Abstract: Detecting an attempted theft of information stored in an RFID-enabled card, including: receiving, by a theft detection module, a transaction request, the transaction request including RFID-enabled card information; determining, by the theft detection module, that the RFID-enabled card information is mock card information, wherein mock card information is provided to an RFID reader by an RFID tag exterior to an RFID shield of an RFID-enabled card security enclosure responsive to an RFID request directed at the security enclosure; and responsive to determining that the RFID-enabled card information is mock card information, initiating, by the theft detection module, one or more security actions.Type: GrantFiled: October 27, 2016Date of Patent: October 6, 2020Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Patent number: 10791628Abstract: A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.Type: GrantFiled: July 3, 2019Date of Patent: September 29, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Patent number: 10554347Abstract: Low latency corrupt data tagging on a cross-chip link including receiving, from the cross-chip link, a control flit comprising a virtual channel identifier for an incoming data flit; storing the virtual channel identifier in a data pipeline and a bad data indicator (BDI) pipeline; receiving, from the cross-chip link, the incoming data flit into the data pipeline; moving, based on the virtual channel identifier in the data pipeline, the data flit from the data pipeline into an entry in a virtual channel queue corresponding to the virtual channel identifier; receiving, from the cross-chip link, a BDI for the data flit into the BDI pipeline; and moving, based on the virtual channel identifier in the BDI pipeline, the BDI for the data flit from the BDI pipeline into an entry in a BDI array corresponding to the entry in the virtual channel queue storing the data flit.Type: GrantFiled: November 27, 2017Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen, Curtis C. Wollbrink
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Publication number: 20190327833Abstract: A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.Type: ApplicationFiled: July 3, 2019Publication date: October 24, 2019Inventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Patent number: 10426030Abstract: A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.Type: GrantFiled: April 21, 2017Date of Patent: September 24, 2019Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Publication number: 20190267036Abstract: Performing an operation comprising extracting a first element of encrypted data embedded in a digital recording comprising at least one of audio data and image data captured in a recording environment, generating a first decrypted value, the generating performed by execution of a cryptography algorithm based on a private key and the first element of encrypted data, comparing the first decrypted value and a stored value associated with a first element of the digital recording, and authenticating the digital recording based on the first decrypted value substantially matching the stored value.Type: ApplicationFiled: February 28, 2018Publication date: August 29, 2019Inventors: Chad M. ALBERTSON, Mark S. FREDRICKSON, David G. WHEELER, Scott D. FREI
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Patent number: 10396944Abstract: Low latency corrupt data tagging on a cross-chip link including receiving, from the cross-chip link, a control flit comprising a virtual channel identifier for an incoming data flit; storing the virtual channel identifier in a data pipeline and a bad data indicator (BDI) pipeline; receiving, from the cross-chip link, the incoming data flit into the data pipeline; moving, based on the virtual channel identifier in the data pipeline, the data flit from the data pipeline into an entry in a virtual channel queue corresponding to the virtual channel identifier; receiving, from the cross-chip link, a BDI for the data flit into the BDI pipeline; and moving, based on the virtual channel identifier in the BDI pipeline, the BDI for the data flit from the BDI pipeline into an entry in a BDI array corresponding to the entry in the virtual channel queue storing the data flit.Type: GrantFiled: September 19, 2017Date of Patent: August 27, 2019Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen, Curtis C. Wollbrink
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Publication number: 20190136579Abstract: A lock system and method for alerting a user or other entity that a lock has been or is being tampered with is disclosed. The lock includes at least one enhanced security pin that is electrically isolated from the rest of the lock. When the lock picker attempts to pick the lock a portion of the enhanced security pin contacts either the plug or the outer casing of the lock to complete a circuit with an alert component. The completion of the circuit causes the alert component to generate an alert signal that can be observed by the user or other entity.Type: ApplicationFiled: January 1, 2019Publication date: May 9, 2019Inventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Publication number: 20190089496Abstract: Low latency corrupt data tagging on a cross-chip link including receiving, from the cross-chip link, a control flit comprising a virtual channel identifier for an incoming data flit; storing the virtual channel identifier in a data pipeline and a bad data indicator (BDI) pipeline; receiving, from the cross-chip link, the incoming data flit into the data pipeline; moving, based on the virtual channel identifier in the data pipeline, the data flit from the data pipeline into an entry in a virtual channel queue corresponding to the virtual channel identifier; receiving, from the cross-chip link, a BDI for the data flit into the BDI pipeline; and moving, based on the virtual channel identifier in the BDI pipeline, the BDI for the data flit from the BDI pipeline into an entry in a BDI array corresponding to the entry in the virtual channel queue storing the data flit.Type: ApplicationFiled: November 27, 2017Publication date: March 21, 2019Inventors: CHAD M. ALBERTSON, ERIC J. CAMPBELL, NICHOLAS J. OLLERICH, CHRISTOPHER W. STEFFEN, CURTIS C. WOLLBRINK
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Publication number: 20190089495Abstract: Low latency corrupt data tagging on a cross-chip link including receiving, from the cross-chip link, a control flit comprising a virtual channel identifier for an incoming data flit; storing the virtual channel identifier in a data pipeline and a bad data indicator (BDI) pipeline; receiving, from the cross-chip link, the incoming data flit into the data pipeline; moving, based on the virtual channel identifier in the data pipeline, the data flit from the data pipeline into an entry in a virtual channel queue corresponding to the virtual channel identifier; receiving, from the cross-chip link, a BDI for the data flit into the BDI pipeline; and moving, based on the virtual channel identifier in the BDI pipeline, the BDI for the data flit from the BDI pipeline into an entry in a BDI array corresponding to the entry in the virtual channel queue storing the data flit.Type: ApplicationFiled: September 19, 2017Publication date: March 21, 2019Inventors: CHAD M. ALBERTSON, ERIC J. CAMPBELL, NICHOLAS J. OLLERICH, CHRISTOPHER W. STEFFEN, CURTIS C. WOLLBRINK
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Publication number: 20190009831Abstract: A vehicle with deployable pliable fairing skirts and a controller for controlling deployment of the skirts are provided. The pliable fairing skirts are deployable over openings of wheel wells for the vehicle to provide additional streamlining for the vehicle. The pliable fairing skirts are stowable when the brakes of the vehicle may benefit from additional cooling airflow. The skirts are also stowable when environmental conditions may result in damage to the skirts or when steerable wheels of the vehicle would protrude from the opening.Type: ApplicationFiled: July 7, 2017Publication date: January 10, 2019Inventors: Chad M. ALBERTSON, Eric J. CAMPBELL, Nicholas J. OLLERICH, Christopher W. STEFFEN
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Patent number: 10167655Abstract: A lock system and method for alerting a user or other entity that a lock has been or is being tampered with is disclosed. The lock includes at least one enhanced security pin that is electrically isolated from the rest of the lock. When the lock picker attempts to pick the lock a portion of the enhanced security pin contacts either the plug or the outer casing of the lock to complete a circuit with an alert component. The completion of the circuit causes the alert component to generate an alert signal that can be observed by the user or other entity.Type: GrantFiled: January 25, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Publication number: 20180310403Abstract: A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.Type: ApplicationFiled: April 21, 2017Publication date: October 25, 2018Inventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Publication number: 20180209172Abstract: A lock system and method for alerting a user or other entity that a lock has been or is being tampered with is disclosed. The lock includes at least one enhanced security pin that is electrically isolated from the rest of the lock. When the lock picker attempts to pick the lock a portion of the enhanced security pin contacts either the plug or the outer casing of the lock to complete a circuit with an alert component. The completion of the circuit causes the alert component to generate an alert signal that can be observed by the user or other entity.Type: ApplicationFiled: January 25, 2017Publication date: July 26, 2018Inventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Publication number: 20180209173Abstract: A lock system and method for alerting a user or other entity that a lock has been or is being tampered with is disclosed. The lock includes at least one enhanced security pin that is electrically isolated from the rest of the lock. When the lock picker attempts to pick the lock a portion of the enhanced security pin contacts either the plug or the outer casing of the lock to complete a circuit with an alert component. The completion of the circuit causes the alert component to generate an alert signal that can be observed by the user or other entity.Type: ApplicationFiled: August 24, 2017Publication date: July 26, 2018Inventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Patent number: 10030416Abstract: A lock system and method for alerting a user or other entity that a lock has been or is being tampered with is disclosed. The lock includes at least one enhanced security pin that is electrically isolated from the rest of the lock. When the lock picker attempts to pick the lock a portion of the enhanced security pin contacts either the plug or the outer casing of the lock to complete a circuit with an alert component. The completion of the circuit causes the alert component to generate an alert signal that can be observed by the user or other entity.Type: GrantFiled: August 24, 2017Date of Patent: July 24, 2018Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Publication number: 20180121686Abstract: Detecting an attempted theft of information stored in an RFID-enabled card, including: receiving, by a theft detection module, a transaction request, the transaction request including RFID-enabled card information; determining, by the theft detection module, that the RFID-enabled card information is mock card information, wherein mock card information is provided to an RFID reader by an RFID tag exterior to an RFID shield of an RFID-enabled card security enclosure responsive to an RFID request directed at the security enclosure; and responsive to determining that the RFID-enabled card information is mock card information, initiating, by the theft detection module, one or more security actions.Type: ApplicationFiled: October 27, 2016Publication date: May 3, 2018Inventors: CHAD M. ALBERTSON, ERIC J. CAMPBELL, NICHOLAS J. OLLERICH, CHRISTOPHER W. STEFFEN