Patents by Inventor Chad Tsai
Chad Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8060676Abstract: The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.Type: GrantFiled: May 11, 2006Date of Patent: November 15, 2011Assignee: VIA Technologies, Inc.Inventors: Chau-Chad Tsai, Chi-Che Tsai, Chih-kuo Kao
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Patent number: 7805567Abstract: A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.Type: GrantFiled: September 13, 2007Date of Patent: September 28, 2010Assignee: Via Technologies, Inc.Inventors: Chun-Yuan Su, Chau-Chad Tsai, Jiin Lai
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Patent number: 7594058Abstract: The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled to said first port-arbiter. The first URD logic includes an onboard range table and a PCI-E device range table for detecting the data of onboard access or peer-to-peer access. The microprocessor receives and processes the data from the first URD logic for said onboard access. The DARD logic receives the data from the microprocessor. The DARD logic decodes a device range of a downstream request of the data. The device arbiter is coupled to the DARD logic and the first URD logic for dispatching the data to one of the first PCI-E port.Type: GrantFiled: November 7, 2005Date of Patent: September 22, 2009Assignee: Via Technologies, Inc.Inventors: Peter Chia, Chad Tsai, Jiin Lai, Edward Su, Chih-Kuo Kao
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Patent number: 7472232Abstract: Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the central processing unit (CPU). While serving a peripheral of single virtual channel utilizing a chipset supporting multiple virtual channels, the present invention assigns accessing requests to different processing queues according to their snooping/non-snooping attributes, such that reading/non-snooping requests are directly routed to a system memory. Also responses from system memory and CPU are buffered in the chipset respectively by utilizing buffer resources of different virtual channels. And by applying accessing routing dispatch, data accessing efficiency can be increased.Type: GrantFiled: September 9, 2005Date of Patent: December 30, 2008Assignee: VIA Technologies Inc.Inventors: Andrew Su, Jiin Lai, Chad Tsai
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Publication number: 20080104320Abstract: A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.Type: ApplicationFiled: September 13, 2007Publication date: May 1, 2008Applicant: VIA TECHNOLOGIES, INC.Inventors: Chun-Yuan Su, Chau-Chad Tsai, Jiin Lai
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Publication number: 20070106826Abstract: The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled to said first port-arbiter. The first URD logic includes an onboard range table and a PCI-E device range table for detecting the data of onboard access or peer-to-peer access. The microprocessor receives and processes the data from the first URD logic for said onboard access. The DARD logic receives the data from the microprocessor. The DARD logic decodes a device range of a downstream request of the data. The device arbiter is coupled to the DARD logic and the first URD logic for dispatching the data to one of the first PCI-E port.Type: ApplicationFiled: November 7, 2005Publication date: May 10, 2007Inventors: Peter Chia, Chad Tsai, Jiin Lai, Edward Su, Chih-Kuo Kao
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Publication number: 20070011390Abstract: A method and related apparatus used for controlling a peripheral device to transfer data to a bus. The peripheral device has a bus interface circuit and a controller. The method includes storing data outputted from the controller into a first storage block of the bus interface circuit, utilizing the bus interface circuit to simultaneously control the first storage block to output its stored data to the bus and control a second storage block of the bus interface circuit to store data outputted from the controller, and utilizing the bus interface circuit to control the second storage block to output its stored data to the bus.Type: ApplicationFiled: September 13, 2006Publication date: January 11, 2007Inventors: Jiin Lai, Chad Tsai, Ju Zhang, Andrew Chuang, Andrew Su
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Patent number: 7136955Abstract: An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.Type: GrantFiled: November 3, 2004Date of Patent: November 14, 2006Assignee: Via Technologies, Inc.Inventors: Chun-Yuan Su, Jiin Lai, Chau-Chad Tsai, Chi-Che Tsai
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Patent number: 7124214Abstract: A method and related apparatus used for controlling a peripheral device to transfer data to a bus. The peripheral device has a bus interface circuit and a controller. The method includes storing data outputted from the controller into a first storage block of the bus interface circuit, utilizing the bus interface circuit to simultaneously control the first storage block to output its stored data to the bus and control a second storage block of the bus interface circuit to store data outputted from the controller, and utilizing the bus interface circuit to control the second storage block to output its stored data to the bus.Type: GrantFiled: January 14, 2004Date of Patent: October 17, 2006Assignee: VIA Technologies Inc.Inventors: Jiin Lai, Chad Tsai, Ju Zhang, Andrew Chuang, Andrew Su
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Publication number: 20060206644Abstract: The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.Type: ApplicationFiled: May 11, 2006Publication date: September 14, 2006Inventors: Chau-Chad Tsai, Chi-Che Tsai, Chih-kuo Kao
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Patent number: 7107373Abstract: The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.Type: GrantFiled: October 25, 2002Date of Patent: September 12, 2006Assignee: Via Technologies, Inc.Inventors: Chau-Chad Tsai, Chi-Che Tsai, Chih-Kuo Kao
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Patent number: 7051148Abstract: A data transmission sequencing method is disclosed. A data read operation from a primary bus to a secondary bus can be executed without having to wait for the complete transfer of write data stored in posted write buffer transferring to the primary bus, as long as the secondary bus is not in use. In the mean time of the primary bus issues a read operation to the secondary bus, the secondary bus can issues write operation to the bridging device when the secondary bus is not in use. Similarly, there is no need to wait for the completion of read operation. With this type of data transmission sequencing mechanism, idle sessions in a conventional transmission sequencing method are eliminated leading to a higher data transmission rate.Type: GrantFiled: January 22, 2002Date of Patent: May 23, 2006Assignee: VIA Technologies, Inc.Inventors: Jiin Lai, Chau-Chad Tsai, Chi-Che Tsai, Wen-Hao Chuang, Chun-Yuan Su
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Publication number: 20060085606Abstract: Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the central processing unit (CPU). While serving a peripheral of single virtual channel utilizing a chipset supporting multiple virtual channels, the present invention assigns accessing requests to different processing queues according to their snooping/non-snooping attributes, such that reading/non-snooping requests are directly routed to system memory. Also responses from system memory and CPU will be buffered in the chipset respectively utilizing buffer resources of different virtual channels. By applying accessing routing dispatch, data accessing efficiency efficient will be increased.Type: ApplicationFiled: September 9, 2005Publication date: April 20, 2006Inventors: Andrew Su, Jiin Lai, Chad Tsai
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Patent number: 6941398Abstract: A processing method, a chip set and a controller for supporting message signaled interrupt. A memory write transaction on a PCI bus is monitored. When the address of the system memory specified in the interrupt message of the write transaction is located at a range of a reserved interrupt address, the interrupting service sequence is performed. The reserved interrupt address is located in an address of a system memory. Thus, the data to be processed and the system-specified message are written in the buffer and arranged in sequence. The problem of “write buffer latency” is resolved, and is irrelevant to the level of the PCI bus. Many system specified messages can be stored in the system memory, so that multiple system message signaled interrupts issue from different peripheral components can be processed in the same interrupt service routine.Type: GrantFiled: April 4, 2001Date of Patent: September 6, 2005Assignee: Via Technologies, Inc.Inventors: Jiin Lai, Chau-Chad Tsai, Sheng-Chang Peng, Min-Hung Chen, Meng-Cheng Ku, Huei-Li Chou
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Patent number: 6934789Abstract: A bus data interface, structure and method for transmitting the data of a PCI bus is disclosed. The bus data interface comprises a high-bit transmitting buffer, a low-bit transmitting buffer, a multiplexer, a strobe generator, and a data distributor. The strobe generator utilizes the bus request signal and bus grant signal to transmit a data strobe signal in response to the PCI clock. According to the rising edge and falling edge of the data strobe signal, the data distributor retrieves data according to the data strobe signal. Further, the invention is compatible with the original PCI bus and allows the PCI bus to transmit data with a dual speed.Type: GrantFiled: June 27, 2001Date of Patent: August 23, 2005Assignee: VIA Technologies, Inc.Inventors: Sheng-Chang Peng, Chau-Chad Tsai, Hsuan-Yi Wang, Chi-Che Tsai
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Patent number: 6925517Abstract: A bus for supporting plural signal line configurations and the method to switch it, used to operate in a bus between the control chips to maintain its operation flexibility. When the data transfer load in between the control chips is suitable for the bi-direction transfer, the signal line configuration of the bi-direction transfer is selected. When the direction of the bi-direction transfer switches frequently, the other signal line configuration is selected. That is, the bus signal lines are divided into two parts, each part is in charge of the data transfer in each uni-direction to avoid the turn around cycle that impacts the transfer performance.Type: GrantFiled: April 3, 2003Date of Patent: August 2, 2005Assignee: VIA Technologies, Inc.Inventors: Sheng-Chang Peng, Chau-Chad Tsai, Chih-kuo Kao, Chi-Che Tsai
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Publication number: 20050097254Abstract: An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter.Type: ApplicationFiled: November 3, 2004Publication date: May 5, 2005Inventors: Chun-Yuan Su, Jiin Lai, Chau-Chad Tsai, Chi-Che Tsai
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Patent number: 6836829Abstract: A peripheral device interface control chip having a cache system therein and a method of synchronization data transmission between the cache system and an external device in a computer system. The cache system and data synchronization method can be applied to the peripheral device interface control chip having a data buffer and a peripheral device interface controller. The data buffer is located inside the control chip for holding data stream read from a memory unit so that data required by the peripheral device is provided. When the data stream is still valid, the data stream is retained. The peripheral device interface controller is installed inside the control chip. The peripheral device interface controller detects if the data stream inside the data buffer includes the data required by the peripheral device and whether the data stream is still valid or not.Type: GrantFiled: May 9, 2001Date of Patent: December 28, 2004Assignee: VIA Technologies, Inc.Inventors: Chau-Chad Tsai, Chi-Che Tsai, Chen-Ping Yang
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Publication number: 20040215866Abstract: A bus for supporting plural signal line configurations and the method to switch it, used to operate in a bus between the control chips to maintain its operation flexibility. When the data transfer load in between the control chips is suitable for the bi-direction transfer, the signal line configuration of the bi-direction transfer is selected. When the direction of the bi-direction transfer switches frequently, the other signal line configuration is selected. That is, the bus signal lines are divided into two parts, each part is in charge of the data transfer in each uni-direction to avoid the turn around cycle that impacts the transfer performance.Type: ApplicationFiled: April 3, 2003Publication date: October 28, 2004Inventors: Sheng-Chang Peng, Chau-Chad Tsai, Chih-kuo Kao, Chi-Che Tsai
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Publication number: 20040193750Abstract: A method and related apparatus used for controlling a peripheral device to transfer data to a bus. The peripheral device has a bus interface circuit and a controller. The method includes storing data outputted from the controller into a first storage block of the bus interface circuit, utilizing the bus interface circuit to simultaneously control the first storage block to output its stored data to the bus and control a second storage block of the bus interface circuit to store data outputted from the controller, and utilizing the bus interface circuit to control the second storage block to output its stored data to the bus.Type: ApplicationFiled: January 14, 2004Publication date: September 30, 2004Inventors: Jiin Lai, Chad Tsai, Ju Zhang, Andrew Chuang, Andrew Su