Abstract: In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.

Abstract: In a general aspect, an integrated quantum circuit includes a first substrate and a second substrate. The first substrate includes a first surface and a recess formed in the first substrate along the first surface. The recess has a recess surface and is configured to enclose a quantum circuit element. The first substrate includes a first electrically-conductive layer disposed on the first surface and covering at least a portion of the recess surface. The first electrically-conductive layer includes a first superconducting material. The second substrate includes a second surface and a quantum circuit element. The second substrate includes a second electrically-conductive layer on the second surface that includes a second superconducting material. The first substrate is adjacent the second substrate to enclose the quantum circuit device within the recess. The first electrically-conductive layer of the first substrate is electrically-coupled to the second electrically-coupled layer of the second substrate.

Abstract: In some aspects, a hybrid quantum-classical computing platform may comprise: a first quantum processor unit (QPU); a second QPU; and a shared classical memory, the shared classical memory being connected to both the first QPU and the second QPU, wherein the shared classical memory is configured to share data between the first QPU and the second QPU. In some embodiments, the first QPU operates at a higher repetition rate and/or clock rate than the second QPU and the second QPU operates with a higher fidelity than the first QPU.

Abstract: In some aspects, a quantum computing system includes a multi-dimensional array of qubit devices. Coupler devices reside at intervals between neighboring pairs of the qubit devices in the multi-dimensional array. Each coupler device is configured to produce an electromagnetic interaction between one of the neighboring pairs of qubit devices. In some cases, each qubit device has a respective qubit operating frequency that is independent of an offset electromagnetic field experienced by the qubit device, and the coupling strength of the electromagnetic interaction provided by each coupler device varies with an offset electromagnetic field experienced by the coupler device. In some cases, readout devices are each operably coupled to a single, respective qubit device to produce qubit readout signals that indicate the quantum state of the qubit device.

Abstract: In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

Abstract: In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

Abstract: In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.

Abstract: In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.

Abstract: In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

Abstract: In a general aspect, a quantum computing method is described. In some aspects, a control system in a quantum computing system assigns subsets of qubit devices in a quantum processor to respective cores. The control system identifies boundary qubit devices residing between the cores in the quantum processor and generates control sequences for each respective core. A signal delivery system in communication with the control system and the quantum processor receives control signals to execute the control sequences, and the control signals are applied to the respective cores in the quantum processor.

Abstract: In some aspects, a heterogeneous computing system includes a quantum processor unit and a classical processor unit. In some instances, variables defined by a computer program are stored in a classical memory in the heterogeneous computing system. The computer program is executed in the heterogeneous computing system by operation of the quantum processor unit and the classical processor unit. Instructions are generated for the quantum processor by a host processor unit based on values of the variables stored in the classical memory. The instructions are configured to cause the quantum processor unit to perform a data processing task defined by the computer program. The values of the variables are updated in the classical memory based on output values generated by the quantum processor unit. The classical processor unit processes the updated values of the variables.

Abstract: In a general aspect, a quantum process for execution by a quantum processor is generated. In some instances, test data representing a test output of a quantum process are obtained. The test data are obtained based on a value assigned to a variable parameter of the quantum process. An objective function is evaluated based on the test data, and an updated value is assigned to the variable parameter based on the evaluation of the objective function. The quantum process is provided for execution by a quantum processor, and the quantum process provided for execution has the updated value assigned to the variable parameter.

Abstract: In a general aspect, information is encoded in data qubits in a three-dimensional device lattice. The data qubits reside in multiple layers of the three-dimensional device lattice, and each layer includes a respective two-dimensional device lattice. A three-dimensional color code is applied in the three-dimensional device lattice to detect errors in the data qubits residing in the multiple layers. A two-dimensional color code is applied in the two-dimensional device lattice in each respective layer to detect errors in one or more of the data qubits residing in the respective layer.

Abstract: In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.

Abstract: In a general aspect, an integrated quantum circuit includes a first substrate and a second substrate. The first substrate includes a first surface and a recess formed in the first substrate along the first surface. The recess has a recess surface and is configured to enclose a quantum circuit element. The first substrate includes a first electrically-conductive layer disposed on the first surface and covering at least a portion of the recess surface. The first electrically-conductive layer includes a first superconducting material. The second substrate includes a second surface and a quantum circuit element. The second substrate includes a second electrically-conductive layer on the second surface that includes a second superconducting material. The first substrate is adjacent the second substrate to enclose the quantum circuit device within the recess. The first electrically-conductive layer of the first substrate is electrically-coupled to the second electrically-coupled layer of the second substrate.

Abstract: In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

Abstract: In a general aspect, a quantum program is automatically synthesized. In some implementations, artificial intelligence systems are used to generate a quantum program to run on a quantum computer. In some aspects, quantum processor output data are generated by a quantum resource executing an initial version of a quantum program, and quantum state information is computed from the quantum processor output data. Neural network input data, which include the quantum state information and a representation of a problem to be solved by the quantum program, are provided to a neural network. Neural network output data are generated by the neural network processing the neural network input data. A quantum logic gate is selected based on the neural network output data. An updated version of the quantum program that includes the selected quantum logic gate is generated.

Abstract: In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.

Abstract: In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.

Abstract: A quantum computing system that includes a quantum circuit device having at least one operating frequency; a first substrate having a first surface on which the quantum circuit device is disposed; a second substrate having a first surface that defines a recess of the second substrate, the first and second substrates being arranged such that the recess of the second substrate forms an enclosure that houses the quantum circuit device; and an electrically conducting layer that covers at least a portion of the recess of the second substrate.