Patents by Inventor Chad W. Fulk

Chad W. Fulk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11817521
    Abstract: In one aspect, a method includes forming an electrical path between p-type mercury cadmium telluride and a metal layer. The forming of the electrical path includes depositing a layer of polycrystalline p-type silicon directly on to the p-type mercury cadmium telluride and forming the metal layer on the layer of polycrystalline p-type silicon. In another aspect, an apparatus includes an electrical path. The electrical path includes a p-type mercury cadmium telluride layer, a polycrystalline p-type silicon layer in direct contact with the p-type mercury cadmium telluride layer, a metal silicide in direct contact with the polycrystalline p-type silicon layer, and an electrically conductive metal on the metal silicide. In operation, holes, indicative of electrical current on the electrical path, flow from the p-type mercury cadmium telluride layer to the electrically conductive metal.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: November 14, 2023
    Assignee: Raytheon Company
    Inventors: Andrew Clarke, David R. Rhiger, Chad W. Fulk, Stuart B. Farrell, James Pattison, Jeffrey M. Peterson, Chad M. Althouse
  • Publication number: 20230082114
    Abstract: In one aspect, a method includes forming an electrical path between p-type mercury cadmium telluride and a metal layer. The forming of the electrical path includes depositing a layer of polycrystalline p-type silicon directly on to the p-type mercury cadmium telluride and forming the metal layer on the layer of polycrystalline p-type silicon. In another aspect, an apparatus includes an electrical path. The electrical path includes a p-type mercury cadmium telluride layer, a polycrystalline p-type silicon layer in direct contact with the p-type mercury cadmium telluride layer, a metal silicide in direct contact with the polycrystalline p-type silicon layer, and an electrically conductive metal on the metal silicide. In operation, holes, indicative of electrical current on the electrical path, flow from the p-type mercury cadmium telluride layer to the electrically conductive metal.
    Type: Application
    Filed: September 15, 2021
    Publication date: March 16, 2023
    Applicant: Raytheon Company
    Inventors: Andrew Clarke, David R. Rhiger, Chad W. Fulk, Stuart B. Farrell, James Pattison, Jeffrey M. Peterson, Chad M. Althouse
  • Patent number: 10418406
    Abstract: Aspects and examples described herein provide a hybrid imaging sensor chip assembly for reducing undesired radiative transfer between a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC) and an optical detector, and methods of manufacturing a hybrid imaging sensor chip assembly. In one example, a hybrid imaging sensor chip assembly includes an optical detector configured to collect electromagnetic radiation incident thereon, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC), and a radiation-shielding wafer interposed between the optical detector and the CMOS ROIC, the radiation-shielding wafer including a plurality of through wafer vias (TWVs) electrically coupled to the optical detector and the CMOS ROIC, the radiation-shielding wafer being positioned to prevent radiative transfer between the CMOS ROIC and the optical detector.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 17, 2019
    Assignee: RAYTHEON COMPANY
    Inventors: Sean P. Kilcoyne, John L. Vampola, Barry M. Starr, Chad W. Fulk, Christopher L. Mears, John J. Drab
  • Publication number: 20180190705
    Abstract: Aspects and examples described herein provide a hybrid imaging sensor chip assembly for reducing undesired radiative transfer between a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC) and an optical detector, and methods of manufacturing a hybrid imaging sensor chip assembly. In one example, a hybrid imaging sensor chip assembly includes an optical detector configured to collect electromagnetic radiation incident thereon, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC), and a radiation-shielding wafer interposed between the optical detector and the CMOS ROIC, the radiation-shielding wafer including a plurality of through wafer vias (TWVs) electrically coupled to the optical detector and the CMOS ROIC, the radiation-shielding wafer being positioned to prevent radiative transfer between the CMOS ROIC and the optical detector.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 5, 2018
    Inventors: Sean P. Kilcoyne, John L. Vampola, Barry M. Starr, Chad W. Fulk, Christopher L. Mears, John J. Drab
  • Patent number: 9704907
    Abstract: An electro-optical sensor chip assembly (SCA) is provided and includes a read-out integrated circuit (ROIC), a detector including a substrate, a buffer layer, a pixel layer and an array of pixels disposed in the pixel layer and an interconnect layer interposed between the ROIC and the pixel layer and comprising cold welded interconnect posts respectively extendible to the ROIC from the pixels. The detector is penetrable by visible wavelength light propagating from a direct view window formed in the substrate and the buffer layer to one or more of the pixels.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: July 11, 2017
    Assignee: RAYTHEON COMPANY
    Inventors: Jay R. Neumann, Peter M. Randolph, Chad W. Fulk