Abstract: A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. The memory device further includes a write shifter configured to receive a first write command of the write commands and to shift the first command through the write shifter. The write shifter is also configured to cause the input buffer to be disabled after a first threshold of clock cycles when the first write command has shifted through the write shifter. The write shifter is additionally configured to receive a second write command and prevent the input buffer from being re-enabled until the second write command has shifted through a second threshold of stages of the write shifter.

Abstract: Systems and methods described herein provide decision feedback equalizer (DFE) circuitry that includes one or more phases. The one or more phases receive bit feedback at respective inputs of the phases. The DFE circuitry also may include variable reset circuitry. The variable reset circuitry may reset voltages of the bit feedback at inputs of each of the phases. The variable reset circuitry is configured to change its reset frequency between resets.

Abstract: Systems and methods described herein provide decision feedback equalizer (DFE) circuitry that includes one or more phases. The one or more phases receive bit feedback at respective inputs of the phases. The DFE circuitry also may include variable reset circuitry. The variable reset circuitry may reset voltages of the bit feedback at inputs of each of the phases. The variable reset circuitry is configured to change its reset frequency between resets.

Abstract: Systems and methods are provided that include an interamble data strobe (DQS) counter configured to count cycles between write operations. The interamble DQS counter includes a decision feedback equalizer (DFE) reset mask circuit configured to generate a DFE reset enable signal and a DFE reset timing generator configured to generate timing signals for the DFE reset. The systems and methods also include a DFE reset generator configured to receive the DFE reset enable signal and the timing signals from the interamble DQS counter, to use the DFE reset enable signal and the timing signals to generate DFE reset signals for a plurality of DQS phases; and to transmit the DFE reset signals to the plurality of DQS phases.

Abstract: Systems and methods are provided that include an interamble data strobe (DQS) counter configured to count cycles between write operations. The interamble DQS counter includes a decision feedback equalizer (DFE) reset mask circuit configured to generate a DFE reset enable signal and a DFE reset timing generator configured to generate timing signals for the DFE reset. The systems and methods also include a DFE reset generator configured to receive the DFE reset enable signal and the timing signals from the interamble DQS counter, to use the DFE reset enable signal and the timing signals to generate DFE reset signals for a plurality of DQS phases; and to transmit the DFE reset signals to the plurality of DQS phases.

Abstract: At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal. If the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal. If the third transistor is not activated, the pre-driver logic provides the output signal.

Abstract: At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal. If the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal. If the third transistor is not activated, the pre-driver logic provides the output signal.

Abstract: At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal. If the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal. If the third transistor is not activated, the pre-driver logic provides the output signal.

Abstract: At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal. If the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal. If the third transistor is not activated, the pre-driver logic provides the output signal.

Abstract: A method and circuitry for alleviating the adverse effect of variable read decode propagation delays and variable output circuitry propagation delays on the read latency, and specifically for generating output enable signals at an appropriate time in light of such variable delays, is disclosed. In one embodiment, a first time domain as specified by an internal clock is delayed by the propagation delay of the read decoder block plus the propagation delay of the output circuitry via a model to create a second time domain which lags the first time domain. Processing in the second time domain associates the internal read command with a particular external clock cycle, and accounts for the specified read latency of the device. The output of such second time domain processing is a signal indicative of which external cycle should be used to enable the outputs. This signal is then converted back into the first timing domain by latches which lead the second timing domain.