Abstract: A method for restricting write cycles to a storage device includes tracking a first count of a first set of writes to memory executed by a first subsystem of a computing device and, further, determining that the first count meets a write threshold of the first subsystem. The method includes determining that blocking criteria are met by the first subsystem based on the first count exceeding the write threshold of the first subsystem and, further, determining that blocking criteria are not met by a second subsystem of the computing device. The method includes blocking the first set of writes from being synchronized to the storage device, based on the blocking criteria being met by the first subsystem, and synchronizing memory contents of the second subsystem to the storage device, based on the blocking criteria not being met by the second subsystem.

Abstract: A method for restricting write cycles to a storage device includes tracking a first count of a first set of writes to memory executed by a first subsystem of a computing device and, further, determining that the first count meets a write threshold of the first subsystem. The method includes determining that blocking criteria are met by the first subsystem based on the first count exceeding the write threshold of the first subsystem and, further, determining that blocking criteria are not met by a second subsystem of the computing device. The method includes blocking the first set of writes from being synchronized to the storage device, based on the blocking criteria being met by the first subsystem, and synchronizing memory contents of the second subsystem to the storage device, based on the blocking criteria not being met by the second subsystem.

Abstract: Aspects of the present disclosure are directed toward receiver devices and methods of using receiver devices. One such method can include converting, using an analog-to-digital converter (ADC), and an analog input signal from power distribution lines that carry power using alternating current (AC) to a digital form. This input digital signal can be an oversampled digital signal, where the digital signal is oversampled relative to downstream processing (e.g., FFT-based processing). A processing circuit(s) can then be used to decimate the input digital signal according to a decimation rate. A reference signal can be generated by the processing circuit that is responsive to the decimation rate. The processing circuit can also be used to detect a change in a phase difference between the AC and reference signal and to modify, in response to detecting a change in the phase difference, the decimation rate to counteract the detected change in the phase difference.

Abstract: Aspects of the present disclosure are also directed towards a method that includes maintaining a transmission period which has a start time and an end time synchronized to metrological time. Further, this method, in response to the start time, begins transmission of a frame, which includes a plurality of symbols. This transmission occurs over power distribution lines that carry power using alternating current (AC). This method also includes synchronizing a transmission time for each symbol of the plurality of symbols according to a time-based parameter of the AC. In response to reaching an end of the frame, a synchronization symbol period is determined for a synchronization symbol, as a function of the transmission times, for the plurality of symbols and time from the end of the frame to the end time. The synchronization symbol is then transmitted on the power distribution lines.

Abstract: Particular embodiments are directed towards a method for communicating time-based data in a power line communication system. The communication system utilized in the method includes: a command center; a collector device; and a plurality of endpoint devices. The method includes communicating, from the collector device, downstream data to the plurality of endpoint devices. This downstream communication utilizes a communication protocol that is relative to a collector network time, and is over a set of power distribution lines carrying alternating current (AC). The collector network time uses the local oscillator. The AC zero-crossing event can be used as a time base for other versions of the network time. Conceptually, the AC can be thought of as acting as a reference clock for maintaining these other network times, although the clocking function can be carried out in the digital realm, e.g., using a digital-signal processor (DSP).

Abstract: Aspects of the present disclosure are directed towards communications over current-carrying power distribution lines. In accordance with one or more embodiments, respective sets of utility-based data indicative of a reading of utility usage taken at different times are communicated. First sets of the data corresponding to readings taken during a first time period are communicated and, thereafter, second sets of the data corresponding to readings taken during a second time period are communicated and interleaved with portions of error correction code (ECC) data. Prior to receiving at least some of the ECC data, the first sets of data are interpreted and access is provided to the interpreted data. After all of the ECC data has been received, the ECC data is used to verify the first sets of data, correct the first sets of data, and access to is provided to the verified first sets of data.

Abstract: Aspects of the present disclosure are directed toward receiver devices and methods of using receiver devices. One such method can include converting, using an analog-to-digital converter (ADC), and an analog input signal from power distribution lines that carry power using alternating current (AC) to a digital form. This input digital signal can be an oversampled digital signal, where the digital signal is oversampled relative to downstream processing (e.g., FFT-based processing). A processing circuit(s) can then be used to decimate the input digital signal according to a decimation rate. A reference signal can be generated by the processing circuit that is responsive to the decimation rate. The processing circuit can also be used to detect a change in a phase difference between the AC and reference signal and to modify, in response to detecting a change in the phase difference, the decimation rate to counteract the detected change in the phase difference.

Abstract: Aspects of the present disclosure are also directed towards a method that includes maintaining a transmission period which has a start time and an end time synchronized to metrological time. Further, this method, in response to the start time, begins transmission of a frame, which includes a plurality of symbols. This transmission occurs over power distribution lines that carry power using alternating current (AC). This method also includes synchronizing a transmission time for each symbol of the plurality of symbols according to a time-based parameter of the AC. In response to reaching an end of the frame, a synchronization symbol period is determined for a synchronization symbol, as a function of the transmission times, for the plurality of symbols and time from the end of the frame to the end time. The synchronization symbol is then transmitted on the power distribution lines.

Abstract: Aspects are directed to communicating data over power distribution lines carrying alternating current, using a communication protocol for communicating data between endpoint devices and an upstream data-collecting device. From first symbols having a plurality of bits, at least two second symbols are generated, the second symbols respectively including different subsets of the bits in the first symbol. Each first symbol is split into second symbols having a predefined bit size for an encoding operation that operates on entire symbols having the predefined bit size (e.g., smaller than the bit size of the first symbols). The second symbols are encoded and combined according to the communication protocol. The encoded symbols are communicated over the power distribution lines based on timing indicated at least in part by the alternating current.

Abstract: Aspects of the present disclosure are directed toward receiver devices and methods of using receiver devices. One such method can include converting, using an analog-to-digital converter (ADC), and an analog input signal from power distribution lines that carry power using alternating current (AC) to a digital form. This input digital signal can be an oversampled digital signal, where the digital signal is oversampled relative to downstream processing (e.g., FFT-based processing). A processing circuit(s) can then be used to decimate the input digital signal according to a decimation rate. A reference signal can be generated by the processing circuit that is responsive to the decimation rate. The processing circuit can also be used to detect a change in a phase difference between the AC and reference signal and to modify, in response to detecting a change in the phase difference, the decimation rate to counteract the detected change in the phase difference.

Abstract: Aspects of the present disclosure are also directed towards a method that includes maintaining a transmission period which has a start time and an end time synchronized to metrological time. Further, this method, in response to the start time, begins transmission of a frame, which includes a plurality of symbols. This transmission occurs over power distribution lines that carry power using alternating current (AC). This method also includes synchronizing a transmission time for each symbol of the plurality of symbols according to a time-based parameter of the AC. In response to reaching an end of the frame, a synchronization symbol period is determined for a synchronization symbol, as a function of the transmission times, for the plurality of symbols and time from the end of the frame to the end time. The synchronization symbol is then transmitted on the power distribution lines.

Abstract: Disclosed are various embodiments for dividing workload in a digital signal processing system. In one embodiment, the system includes at least one analog-to-digital converter configured to receive a three phase analog waveform and a digital waveform. The system can also include a first DSP configured to interface with an external computer and a second DSP configured to receive the digital waveform and isolate a specified frequency range. The system can also include a plurality of DSP's configured to extract specified channels from the specified frequency range and output the extracted channel data.

Abstract: Aspects of the present disclosure are also directed towards a method that includes maintaining a transmission period which has a start time and an end time synchronized to metrological time. Further, this method, in response to the start time, begins transmission of a frame, which includes a plurality of symbols. This transmission occurs over power distribution lines that carry power using alternating current (AC). This method also includes synchronizing a transmission time for each symbol of the plurality of symbols according to a time-based parameter of the AC. In response to reaching an end of the frame, a synchronization symbol period is determined for a synchronization symbol, as a function of the transmission times, for the plurality of symbols and time from the end of the frame to the end time. The synchronization symbol is then transmitted on the power distribution lines.

Abstract: Aspects of the present disclosure are directed toward receiver devices and methods of using receiver devices. One such method can include converting, using an analog-to-digital converter (ADC), and an analog input signal from power distribution lines that carry power using alternating current (AC) to a digital form. This input digital signal can be an oversampled digital signal, where the digital signal is oversampled relative to downstream processing (e.g., FFT-based processing). A processing circuit(s) can then be used to decimate the input digital signal according to a decimation rate. A reference signal can be generated by the processing circuit that is responsive to the decimation rate. The processing circuit can also be used to detect a change in a phase difference between the AC and reference signal and to modify, in response to detecting a change in the phase difference, the decimation rate to counteract the detected change in the phase difference.

Abstract: Disclosed are various embodiments of an input signal combiner. In one embodiment, a receive stage receives a multi-phase waveform and separates the multi-phase waveform into a plurality of waveforms. Analog-to-digital converters convert the plurality of analog waveforms into at least one digital signal. At least one gain stage adjusts an amplitude of each of the digital signals and combines the amplitude adjusted digital signals into at least one gain adjusted combined signal. A signal extraction stage extracts an inbound signal from the at least one gain adjusted combined signal according to a demodulation scheme.

Abstract: Disclosed are various embodiments for outage detection. In one embodiment, an outage detection system includes a signal sampler configured to sample a signal on a communications link and to determine a noise level and a signal level of the sample. An outage detection system also includes a comparator configured to compare a critical value with a sum of signal and noise of the sample. An outage detection system further includes a binomial probability analyzer configured to calculate a binomial probability of false outage of the sample and the previous N samples.

Abstract: Disclosed are various embodiments for arbitration of memory transfers in a digital signal processing system. In one embodiment, a digital signal processing system includes a plurality of DSP's having an external memory. The DSP's are further configurable to act as a master processor and a slave processor relative to another DSP. The system also includes an arbiter configured to maintain DSP status data and arbitrate requests between master processors and slave processors in the system.

Abstract: Disclosed are various embodiments of an input signal combiner. In one embodiment, a receive stage receives a multi-phase waveform and separates the multi-phase waveform into a plurality of waveforms. Analog-to-digital converters convert the plurality of analog waveforms into at least one digital signal. At least one gain stage adjusts an amplitude of each of the digital signals and combines the amplitude adjusted digital signals into at least one gain adjusted combined signal. A signal extraction stage extracts an inbound signal from the at least one gain adjusted combined signal according to a demodulation scheme.

Abstract: Disclosed are various embodiments for arbitration of memory transfers in a digital signal processing system. In one embodiment, a digital signal processing system includes a plurality of DSP's having an external memory. The DSP's are further configurable to act as a master processor and a slave processor relative to another DSP. The system also includes an arbiter configured to maintain DSP status data and arbitrate requests between master processors and slave processors in the system.

Abstract: Disclosed are various embodiments for dividing workload in a digital signal processing system. In one embodiment, the system includes at least one analog-to-digital converter configured to receive a three phase analog waveform and a digital waveform. The system can also include a first DSP configured to interface with an external computer and a second DSP configured to receive the digital waveform and isolate a specified frequency range. The system can also include a plurality of DSP's configured to extract specified channels from the specified frequency range and output the extracted channel data.