Abstract: The present invention relates to a method and apparatus for encoding a displacement video using image tiling. A method for encoding multi-dimensional data according to an embodiment of the present disclosure may comprise: converting the multi-dimensional data into one or more frames with two-dimensional characteristics; generating one or more frame groups by grouping the one or more frames with pre-configured number units; reconstructing frames belonging to each frame group into a tiled frame; and generating a bitstream by encoding the tiled frame. Here, the tiled frame may be constructed with one or more blocks, and each block may be constructed by rearranging pixels existing at the same location in the frames.

Abstract: The present invention relates to a method and apparatus for encoding a displacement video using image tiling. A method for encoding multi-dimensional data according to an embodiment of the present disclosure may comprise: converting the multi-dimensional data into one or more frames with two-dimensional characteristics; generating one or more frame groups by grouping the one or more frames with pre-configured number units; reconstructing frames belonging to each frame group into a tiled frame; and generating a bitstream by encoding the tiled frame. Here, the tiled frame may be constructed with one or more blocks, and each block may be constructed by rearranging pixels existing at the same location in the frames.

Abstract: An image processing method includes obtaining a plurality of main images for a plurality of light field images captured from different viewpoints, generating a depth map representing depth information of the plurality of light field images, based on the plurality of main images, generating a plurality of prediction images for the plurality of light field images, based on the plurality of main images, generating a plurality of residual images representing a difference between the plurality of light field images and the plurality of prediction images, and generating a micro image based on the depth map and the plurality of residual images.

Abstract: The electronic apparatus includes a memory stored with a multiple light field unit (LFU) structure in which a plurality of light fields is arranged in a lattice structure, and a processor configured to, based on a view position within the lattice structure being determined, generate a 360-degree image based on the view position by using the multiple LFU structure, and the processor is configured to select an LFU to which the view position belongs from among the multiple LFU structure, allocate a rendering field-of-view (FOV) in predetermined degrees based on the view position, generate a plurality of view images based on a plurality of light fields comprising the selected LFU and the allocated FOV, and generate the 360-degree image by incorporating the generated plurality of view images.

Abstract: Provided is a hybrid near-memory processing system including a GPU, a PIM-HBM, a CPU, and a main memory. An embedding vector is loaded through the GPU and the PIM-HBM, an embedding table is divided and stored in the main memory and the HBM in a training process for inference of a recommendation system, an embedding lookup operation is performed in the main memory or the HBM according to a location of a necessary embedding vector in an inference process of the recommendation system, an additional embedding manipulation operation is performed in the CPU and the PIM with respect to the embedding vector of which the embedding lookup operation is completed, embedding vectors processed through embedding manipulation are finally concatenated in the PIM to generate an embedding result, and the embedding result is transmitted to the GPU to derive a final inference result through a top multiplayer perceptron (MLP) process.

Abstract: An on-chip bus includes a plurality of switch points including first and second switch points, a plurality of inter-switch links including at least one inter-switch link coupled between the first switch point and the second switch point and configured to communicate data between the first switch point and the second switch point, and a plurality of functional block cores including first and second functional block cores coupled directly to the first switch point and configured to communicate data through the first switch point. Data transmitted from the first functional block core to the second functional block cores may pass through the first switch point without traversing any of the plurality of inter-switch links. Methods for communicating data on an on-chip bus are also disclosed.

Abstract: Provided are a method of creating an optimized tile-switch mapping architecture in an on-chip bus, and a computer readable recording medium for recording the method. The method of creating a tile-switch mapping architecture includes first, second and third calculating steps. The method of creating a tile-switch mapping architecture minimizes the hop distance between cores when the mapping relationship between cores and tiles is determined, to thereby minimize energy consumption and communication delay time in an on-chip bus. Furthermore, the method of creating a tile-switch mapping architecture presents a standard for comparing the optimization of other mapping architectures.

Abstract: There are provided a method of creating an optimized core-tile-switch mapping architecture in an on-chip bus and a computer-readable recording medium for recording the method. The core-tile-switch mapping architecture creating method includes: creating a core communication graph representing the connection relationship between arbitrary cores; creating a Network-on-chip (NOC) architecture including a plurality of switches, a plurality of tiles, and a plurality of links interconnecting the plurality of switches; and mapping the cores to the tiles using a predetermined optimized mapping method to thereby create the optimized core-tile-switch mapping architecture. The optimized mapping method includes first, second, and third calculating steps.

Abstract: There are provided a method of creating an optimized core-tile-switch mapping architecture in an on-chip bus and a computer-readable recording medium for recording the method. The core-tile-switch mapping architecture creating method includes: creating a core communication graph representing the connection relationship between arbitrary cores; creating a Network-on-chip (NOC) architecture including a plurality of switches, a plurality of tiles, and a plurality of links interconnecting the plurality of switches; and mapping the cores to the tiles using a predetermined optimized mapping method to thereby create the optimized core-tile-switch mapping architecture. The optimized mapping method includes first, second, and third calculating steps.

Abstract: Provided are a method of creating an optimized tile-switch mapping architecture in an on-chip bus, and a computer readable recording medium for recording the method. The method of creating a tile-switch mapping architecture includes first, second and third calculating steps. The method of creating a tile-switch mapping architecture minimizes the hop distance between cores when the mapping relationship between cores and tiles is determined, to thereby minimize energy consumption and communication delay time in an on-chip bus. Furthermore, the method of creating a tile-switch mapping architecture presents a standard for comparing the optimization of other mapping architectures.

Abstract: An on-chip bus includes a plurality of switch points including first and second switch points, a plurality of inter-switch links including at least one inter-switch link coupled between the first switch point and the second switch point and configured to communicate data between the first switch point and the second switch point, and a plurality of functional block cores including first and second functional block cores coupled directly to the first switch point and configured to communicate data through the first switch point. Data transmitted from the first functional block core to the second functional block cores may pass through the first switch point without traversing any of the plurality of inter-switch links. Methods for communicating data on an on-chip bus are also disclosed.

Abstract: A bus arrangement is provided including a master device and a slave device. A master converts a read command into a write command and sends the write command through a bus network within the bus arrangement and a slave device converts the write command back to the read command and sends a response. The response is sent on a bus not included within the bus network, thereby reducing a response delay time between the transmission of the read command and the response to the read command.