Abstract: An on-chip bus includes a plurality of switch points including first and second switch points, a plurality of inter-switch links including at least one inter-switch link coupled between the first switch point and the second switch point and configured to communicate data between the first switch point and the second switch point, and a plurality of functional block cores including first and second functional block cores coupled directly to the first switch point and configured to communicate data through the first switch point. Data transmitted from the first functional block core to the second functional block cores may pass through the first switch point without traversing any of the plurality of inter-switch links. Methods for communicating data on an on-chip bus are also disclosed.

Abstract: Provided are a method of creating an optimized tile-switch mapping architecture in an on-chip bus, and a computer readable recording medium for recording the method. The method of creating a tile-switch mapping architecture includes first, second and third calculating steps. The method of creating a tile-switch mapping architecture minimizes the hop distance between cores when the mapping relationship between cores and tiles is determined, to thereby minimize energy consumption and communication delay time in an on-chip bus. Furthermore, the method of creating a tile-switch mapping architecture presents a standard for comparing the optimization of other mapping architectures.

Abstract: There are provided a method of creating an optimized core-tile-switch mapping architecture in an on-chip bus and a computer-readable recording medium for recording the method. The core-tile-switch mapping architecture creating method includes: creating a core communication graph representing the connection relationship between arbitrary cores; creating a Network-on-chip (NOC) architecture including a plurality of switches, a plurality of tiles, and a plurality of links interconnecting the plurality of switches; and mapping the cores to the tiles using a predetermined optimized mapping method to thereby create the optimized core-tile-switch mapping architecture. The optimized mapping method includes first, second, and third calculating steps.

Abstract: There are provided a method of creating an optimized core-tile-switch mapping architecture in an on-chip bus and a computer-readable recording medium for recording the method. The core-tile-switch mapping architecture creating method includes: creating a core communication graph representing the connection relationship between arbitrary cores; creating a Network-on-chip (NOC) architecture including a plurality of switches, a plurality of tiles, and a plurality of links interconnecting the plurality of switches; and mapping the cores to the tiles using a predetermined optimized mapping method to thereby create the optimized core-tile-switch mapping architecture. The optimized mapping method includes first, second, and third calculating steps.

Abstract: Provided are a method of creating an optimized tile-switch mapping architecture in an on-chip bus, and a computer readable recording medium for recording the method. The method of creating a tile-switch mapping architecture includes first, second and third calculating steps. The method of creating a tile-switch mapping architecture minimizes the hop distance between cores when the mapping relationship between cores and tiles is determined, to thereby minimize energy consumption and communication delay time in an on-chip bus. Furthermore, the method of creating a tile-switch mapping architecture presents a standard for comparing the optimization of other mapping architectures.

Abstract: An on-chip bus includes a plurality of switch points including first and second switch points, a plurality of inter-switch links including at least one inter-switch link coupled between the first switch point and the second switch point and configured to communicate data between the first switch point and the second switch point, and a plurality of functional block cores including first and second functional block cores coupled directly to the first switch point and configured to communicate data through the first switch point. Data transmitted from the first functional block core to the second functional block cores may pass through the first switch point without traversing any of the plurality of inter-switch links. Methods for communicating data on an on-chip bus are also disclosed.

Abstract: A bus arrangement is provided including a master device and a slave device. A master converts a read command into a write command and sends the write command through a bus network within the bus arrangement and a slave device converts the write command back to the read command and sends a response. The response is sent on a bus not included within the bus network, thereby reducing a response delay time between the transmission of the read command and the response to the read command.