Abstract: A leakage current control device of a semiconductor memory device is provided to effectively remove leakage current flowing from a bit line to a word line when a process defect is generated by gate residues of the semiconductor memory device, thereby reducing unnecessary current consumption. In the leakage current control device, the bit line boosted to a voltage level of core voltage/2 is controlled at a ground voltage level during a precharge period to remove unnecessary leakage current flowing from the bit line to a word line bridge.

Abstract: Provided is directed to a semiconductor memory device including a control path for enabling a sense generator signal for delaying time as long as a bitline sense amplifier operates in response to a row active signal and enabling a precharge signal according to the sense generator signal, wherein the control path includes: a first time control unit for varying an enabling time of the sense generator signal by eacn time, according to a special test mode signal for testing the semiconductor memory device and a specific column address; and a second time control unit for varying an enabling time of the precharge signal by each step, according to a special test mode signal for testing the semiconductor memory device and a specific column address.