Patents by Inventor Chae Yeon HWANG

Chae Yeon HWANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11682680
    Abstract: Disclosed are a crystalline oxide semiconductor thin film including a crystalline oxide semiconductor including indium, gallium, and tin, the crystalline oxide semiconductor exhibiting a (009) diffraction peak in an X-ray diffraction spectrum, and a method of forming the same, a thin film transistor and a method of manufacturing the same, a display panel, and an electronic device.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: June 20, 2023
    Assignee: ADRC. CO. KR
    Inventors: Soon Ho Choi, Chae Yeon Hwang, Suhui Lee
  • Publication number: 20230172063
    Abstract: Disclosed are a diode element, a sensor including the same, and an electronic device. The diode element includes a first electrode, a second electrode facing the first electrode, and an active layer between the first electrode and the second electrode, wherein the active layer includes a quantum dot having an energy bandgap of about 0.1 eV to about 1.5 eV and an organic semiconductor having a wider energy bandgap than the quantum dot, and a difference between a HOMO energy level of the quantum dot and a HOMO energy level of the organic semiconductor is less than 1.0 eV.
    Type: Application
    Filed: June 23, 2022
    Publication date: June 1, 2023
    Inventors: Chae Yeon HWANG, Donggyu EO
  • Publication number: 20230154929
    Abstract: A thin film transistor according to an exemplary embodiment includes: a substrate; a semiconductor layer disposed on the substrate and including a channel region, and an input region and an output region disposed on both sides of the channel region and doped with an impurity; a buffer layer disposed between the substrate and the semiconductor layer; a control electrode overlapping the semiconductor layer; a gate insulation layer disposed between the semiconductor layer and the control electrode; and an input electrode connected to the input region and an output electrode connected to the output region, wherein the semiconductor layer includes polysilicon and is crystallized by a blue laser scan.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 18, 2023
    Inventors: Youngbin DO, Chae Yeon HWANG
  • Patent number: 11616086
    Abstract: A thin film transistor panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate and including a first semiconductor layer including a low temperature polysilicon and a first control electrode overlapping the first semiconductor layer; a second transistor disposed on the substrate and including a second semiconductor layer including an oxide semiconductor and a second control electrode overlapping the second semiconductor layer; a first gate insulation layer disposed between the first semiconductor layer and the first control electrode of the first transistor and including a first insulation layer and a second insulation layer; and a second gate insulation layer disposed between the second semiconductor layer and the second control electrode of the second transistor and including the second insulation layer, wherein the density of the first insulation layer may be higher than the density of the second insulation layer, the first semiconductor layer of the f
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: March 28, 2023
    Assignee: ADRC. CO. KR
    Inventors: Duk Young Jeong, Chae Yeon Hwang, Dong Gyu Eo
  • Patent number: 11587952
    Abstract: A thin film transistor according to an exemplary embodiment includes: a substrate; a semiconductor layer disposed on the substrate and including a channel region, and an input region and an output region disposed on both sides of the channel region and doped with an impurity; a buffer layer disposed between the substrate and the semiconductor layer; a control electrode overlapping the semiconductor layer; a gate insulation layer disposed between the semiconductor layer and the control electrode; and an input electrode connected to the input region and an output electrode connected to the output region, wherein the semiconductor layer includes polysilicon and is crystallized by a blue laser scan.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: February 21, 2023
    Assignee: ADRC. CO. KR
    Inventors: Youngbin Do, Chae Yeon Hwang
  • Publication number: 20220208805
    Abstract: Disclosed are a crystallization process of an oxide semiconductor, a method of manufacturing a thin film transistor including the same, a thin film transistor, a display panel, and an electronic device. The crystallization process of an oxide semiconductor includes forming an amorphous oxide semiconductor layer on a substrate, forming a crystallization auxiliary layer including a light absorbing inorganic material on the amorphous oxide semiconductor layer, and annealing the crystallization auxiliary layer to crystallize the amorphous oxide semiconductor layer.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 30, 2022
    Inventors: Soon Ho CHOI, Chae Yeon HWANG, Hyo Min KIM
  • Publication number: 20220208807
    Abstract: Disclosed are a crystalline oxide semiconductor thin film including a crystalline oxide semiconductor including indium, gallium, and tin, the crystalline oxide semiconductor exhibiting a (009) diffraction peak in an X-ray diffraction spectrum, and a method of forming the same, a thin film transistor and a method of manufacturing the same, a display panel, and an electronic device.
    Type: Application
    Filed: March 15, 2021
    Publication date: June 30, 2022
    Inventors: Soon Ho CHOI, Chae Yeon HWANG, Suhui LEE
  • Publication number: 20210272986
    Abstract: A thin film transistor according to an exemplary embodiment includes: a substrate; a semiconductor layer disposed on the substrate and including a channel region, and an input region and an output region disposed on both sides of the channel region and doped with an impurity; a buffer layer disposed between the substrate and the semiconductor layer; a control electrode overlapping the semiconductor layer; a gate insulation layer disposed between the semiconductor layer and the control electrode; and an input electrode connected to the input region and an output electrode connected to the output region, wherein the semiconductor layer includes polysilicon and is crystallized by a blue laser scan.
    Type: Application
    Filed: January 12, 2021
    Publication date: September 2, 2021
    Inventors: Youngbin DO, Chae Yeon HWANG
  • Publication number: 20210210525
    Abstract: A thin film transistor panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate and including a first semiconductor layer including a low temperature polysilicon and a first control electrode overlapping the first semiconductor layer; a second transistor disposed on the substrate and including a second semiconductor layer including an oxide semiconductor and a second control electrode overlapping the second semiconductor layer; a first gate insulation layer disposed between the first semiconductor layer and the first control electrode of the first transistor and including a first insulation layer and a second insulation layer; and a second gate insulation layer disposed between the second semiconductor layer and the second control electrode of the second transistor and including the second insulation layer, wherein the density of the first insulation layer may be higher than the density of the second insulation layer, the first semiconductor layer of the f
    Type: Application
    Filed: December 17, 2020
    Publication date: July 8, 2021
    Inventors: Duk Young JEONG, Chae Yeon HWANG, Dong Gyu EO