Patents by Inventor Chae Deok Lim
Chae Deok Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12505160Abstract: Provided is a method and apparatus for registering metadata regarding a drone image. The apparatus for registering metadata regarding a drone image acquires captured data, and parses metadata from the captured data. The apparatus for registering metadata regarding a drone image generates new metadata using additional information and the parsed metadata, and registers the generated new metadata and the captured data to generate new captured data.Type: GrantFiled: December 29, 2022Date of Patent: December 23, 2025Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Beob Kyun Kim, Chae Deok Lim, Kyung Il Kim, Young Bin Kim, Jin Ah Shin, Duk Kyun Woo, Dong Wan Ryoo, Yoo Jin Lim, Yang Jae Jeong, Su Jung Ha
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Publication number: 20250147857Abstract: Provided is a method of driving an intermittent system, which includes: generating a reference code and a transition code in which a power polling function is added to the reference code, and storing the reference code and the transition code in a memory; executing the reference code; storing storage information including an instruction address of the reference code that is in execution when a power interrupt is received, and calculating an instruction address of the transition code corresponding to the instruction address of the reference code; executing the transition code from the calculated instruction address of the transition code; and performing the power polling added to the transition code.Type: ApplicationFiled: November 5, 2024Publication date: May 8, 2025Inventors: Youngbin KIM, Kwang Yong LEE, Yoojin LIM, Chae Deok LIM, Jung Eun CHA
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Publication number: 20250131155Abstract: Proposed are an apparatus and a method for simulating charge and discharge energy in an intermittent computing system. Specifically, an operation method for simulating power instability in intermittent computing includes receiving at least one selected from a group of energy storage and SBC standard information of an intermittent computing system, energy consumption information for an application program of the intermittent computing system, and illuminance information, and generating an intermittent computing charge and discharge energy scenario model on the basis of the received information, and performing intermittent computing energy simulation on the basis of the generated model, and identifying whether a result of the simulation is appropriate.Type: ApplicationFiled: May 31, 2024Publication date: April 24, 2025Inventors: Kwang Yong LEE, Young Bin KIM, Yoo Jin LIM, Chae Deok LIM, Jung Eun CHA
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Publication number: 20230239548Abstract: Provided is a method and apparatus for registering metadata regarding a drone image. The apparatus for registering metadata regarding a drone image acquires captured data, and parses metadata from the captured data. The apparatus for registering metadata regarding a drone image generates new metadata using additional information and the parsed metadata, and registers the generated new metadata and the captured data to generate new captured data.Type: ApplicationFiled: December 29, 2022Publication date: July 27, 2023Applicant: Electronics and Telecommunications Research InstituteInventors: Beob Kyun KIM, Chae Deok LIM, Kyung Il KIM, Young Bin KIM, Jin Ah SHIN, Duk Kyun WOO, Dong Wan RYOO, Yoo Jin LIM, Yang Jae JEONG, Su Jung HA
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Publication number: 20230121052Abstract: A resource resettable deep neural network accelerator according to an embodiment of the present disclosure includes: a memory layer including a scratchpad memory layer configured to divide deep neural network parameter data (hereinafter, data) in an external memory layer into a plurality of tiles and to load the divided tiles, and a register file memory layer configured to load tiled data of the scratchpad memory layer; and a plurality of cores configured to process an inference operation for the data loaded in the register file memory layer, wherein the memory layer includes a virtual tiling layer added to a certain location for loading the tiled data from a previous memory layer so as to correspond to a specific tiling size.Type: ApplicationFiled: October 14, 2022Publication date: April 20, 2023Applicant: Electronics and Telecommunications Research InstituteInventors: Young Bin KIM, Jin Ah SHIN, Chae Deok LIM, Kyung Il KIM, Beob Kyun KIM, Duk Kyun WOO, Dong Wan RYOO, Yoo Jin LIM, Yang Jae JEONG, Su Jung HA
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Publication number: 20170228241Abstract: Provided herein are an acceleration system and a driving method thereof. The acceleration system includes a configuration memory, and a plurality of processing units which receive works from the configuration memory, perform the received works, and output results of the performed works. Each of the processing units include an n (n is an integer of three or more) number of processing elements which generate an n number of results, and each of which receives one of the works, and a select module which selects, using a majority-vote system, one of the n number of generated results and generates a selected result.Type: ApplicationFiled: February 16, 2016Publication date: August 10, 2017Inventors: Yong Joo KIM, Kyung Hee LEE, Chae Deok LIM
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Patent number: 9729305Abstract: Disclosed are an airplane system including duplex modules, and a control method thereof. The control method of the airplane system includes: receiving, by each of a plurality of duplex modules, a corresponding event command from a client; performing, by a first module, a first event specified by the event command in response to the event command; performing, by a second module different from the first module, a second event specified by the event command after the first event is completed; and returning a first response signal indicating a result of the performance of the first event and a second response signal indicating a result of the performance of the second event to the client, in which the client compares the first response signal and the second response signal, and determines whether the plurality of duplex modules is synchronized or has an error.Type: GrantFiled: February 2, 2015Date of Patent: August 8, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Chang Min Shin, Tae Ho Kim, Chae Deok Lim
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Patent number: 9417904Abstract: A cyber-physical system and a method of monitoring a virtual machine thereof are provided. The cyber-physical system includes a plurality of target controllers that includes middleware operating based on different operating systems and that control different targets, and a system monitor that includes integrated middleware of analyzing and synthesizing information collected from the middleware. First virtual machines corresponding to virtualization of the target controllers and a second virtual machine corresponding to virtualization of the system monitor are independently formed through a virtual machine monitor.Type: GrantFiled: July 10, 2014Date of Patent: August 16, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jin Ah Shin, Taeho Kim, Chae Deok Lim
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Publication number: 20160098289Abstract: An interrupt controller, a system and a method for handling an interrupt under a virtualization environment are provided. The system for handling an interrupt, includes: an interrupt controller, a virtual machine, and a hypervisor which controls activation of the virtual machine, the interrupt controller may receive a physical interrupt from the outside and transmit the physical interrupt to the hypervisor or the virtual machine based on a characteristic of the physical interrupt, the hypervisor may convert the physical interrupt into a virtual interrupt to transmit the virtual interrupt to the virtual machine, and the virtual machine may handle the physical interrupt or the virtual interrupt using a first interrupt handler which is included in the virtual machine.Type: ApplicationFiled: November 12, 2014Publication date: April 7, 2016Inventors: Dong Hyouk LIM, Tae Ho KIM, Chae Deok LIM
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Publication number: 20150331569Abstract: Disclosed are a device for controlling a user interface, which promotes convenience for a user by adjusting a position or an arrangement of a user interface displayed on a screen, and a method of controlling a user interface thereof. A control method of a user interface controlling device includes: detecting a position of a hand of a user; determining whether a disposition of a user interface is appropriate according to the detected position of the hand; and changing a disposition of the user interface so that the user interface is positioned to be close to the detected position of the hand according to a result of the determination.Type: ApplicationFiled: February 12, 2015Publication date: November 19, 2015Inventors: Dong Wook KANG, Tae Ho KIM, Chae Deok LIM
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Publication number: 20150293790Abstract: Provided herein a method for driving a virtual machine, the method including providing a plurality of virtual machines and a virtual machine monitor configured to manage the plurality of virtual machines; generating, by the plurality of virtual machines, memory management information, that is information on memory being used by the plurality of virtual machines; and determining, by the virtual machine monitor, whether or not a virtual machine is a victim virtual machine from which memory needs to be retrieved or whether or not the virtual machine is a beneficiary virtual machine where memory needs to be allocated, based on the memory management information.Type: ApplicationFiled: March 31, 2015Publication date: October 15, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Soo Young KIM, Tae Ho KIM, Chae Deok LIM
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Publication number: 20150256321Abstract: Disclosed are an airplane system including duplex modules, and a control method thereof The control method of the airplane system includes: receiving, by each of a plurality of duplex modules, a corresponding event command from a client; performing, by a first module, a first event specified by the event command in response to the event command; performing, by a second module different from the first module, a second event specified by the event command after the first event is completed; and returning a first response signal indicating a result of the performance of the first event and a second response signal indicating a result of the performance of the second event to the client, in which the client compares the first response signal and the second response signal, and determines whether the plurality of duplex modules is synchronized or has an error.Type: ApplicationFiled: February 2, 2015Publication date: September 10, 2015Inventors: Chang Min SHIN, Tae Ho KIM, Chae Deok LIM
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Publication number: 20150100964Abstract: Provided are an apparatus and method for managing migration of tasks between cores based on a scheduling policy, which can provide optimal environments utilizing multiple cores to the tasks with various characteristics. It is possible to schedule tasks in consideration of different characteristics. In particular, it is possible to continuously secure the performance of the multi-core system in an environment for operating a plurality of application programs. It is also possible to optimally utilize all cores of the multi-core system, thereby flexibly handling dynamic variation in characteristics of tasks.Type: ApplicationFiled: June 5, 2014Publication date: April 9, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Gap Joo NA, Yung Joon JUNG, Chae Deok LIM
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Publication number: 20150082306Abstract: A cyber-physical system and a method of monitoring a virtual machine thereof are provided. The cyber-physical system includes a plurality of target controllers that includes middleware operating based on different operating systems and that control different targets, and a system monitor that includes integrated middleware of analyzing and synthesizing information collected from the middleware. First virtual machines corresponding to virtualization of the target controllers and a second virtual machine corresponding to virtualization of the system monitor are independently formed through a virtual machine monitor.Type: ApplicationFiled: July 10, 2014Publication date: March 19, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Jin Ah SHIN, Taeho KIM, Chae Deok LIM
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Patent number: 8850291Abstract: A data input method of a NAND flash memory includes: determining whether a size of a writing-requested data is less than a reference value; calculating an error correction code (ECC) for the data using a software ECC method when the data size is less than the reference value; and writing the data and the ECC to a data region of the NAND flash memory. A data output method of the NAND flash memory includes: determining whether a size of a reading-requested data is less than a reference value; reading the data and an error correction code (ECC) from the NAND flash memory; calculating an ECC for the read data using a software ECC method when the data size is less than the reference value; and performing an error detection and correction by comparing the calculated ECC and the read ECC.Type: GrantFiled: January 5, 2011Date of Patent: September 30, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Dong Wook Kang, Chae Deok Lim
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Publication number: 20120163628Abstract: An apparatus for reducing digital audio output noise includes: a signal processing unit configured to process digital audio data to output to a speaker; a switching unit configured to mute the speaker; and a control unit configured to monitor the signal processing unit to determine whether a current state is a mute state or not, and control the switching unit according to the determination result.Type: ApplicationFiled: November 4, 2011Publication date: June 28, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Kyung Hee Lee, Chae Deok Lim
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Publication number: 20120159111Abstract: Exemplary embodiments of the present invention can reduce physical memory usage of programs executed in an operating system by immediately releasing an allocated memory region at the time of a request of unloading the memory region if it is determined that the memory region which is allocated by programs executed in the operating system becomes unnecessary. A method for memory management includes making a request of unloading a memory region from programs; reclaiming a physical memory region allocated to the programs; and maintaining a record of the memory region that the programs intend to use.Type: ApplicationFiled: December 20, 2011Publication date: June 21, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Ik-Soon KIM, Chae Deok LIM
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Publication number: 20120159497Abstract: Provided is an adaptive process scheduling method for embedded Linux. The adaptive process scheduling method includes calculating a central processing unit (CPU) occupancy time of each of one or more processes, determining whether or not it is necessary to perform adaptive process scheduling, calculating a predetermined weight to be applied to the CPU occupancy time of each process when it is determined that it is necessary to perform adaptive process scheduling, and applying the predetermined weight and updating the CPU occupancy time of each process when it is determined that it is necessary to perform adaptive process scheduling. Accordingly, the adaptive process scheduling method can improve the performance by omitting an unnecessary context exchange compared to the related art and can dynamically cope with an abrupt increase in the number of processes.Type: ApplicationFiled: December 15, 2011Publication date: June 21, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Dong Hyouk LIM, Yung Joon JUNG, Chae Deok LIM
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Publication number: 20120096333Abstract: A data input method of a NAND flash memory includes: determining whether a size of a writing-requested data is less than a reference value; calculating an error correction code (ECC) for the data using a software ECC method when the data size is less than the reference value; and writing the data and the ECC to a data region of the NAND flash memory. A data output method of the NAND flash memory includes: determining whether a size of a reading-requested data is less than a reference value; reading the data and an error correction code (ECC) from the NAND flash memory; calculating an ECC for the read data using a software ECC method when the data size is less than the reference value; and performing an error detection and correction by comparing the calculated ECC and the read ECC.Type: ApplicationFiled: January 5, 2011Publication date: April 19, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Dong Wook KANG, Chae Deok LIM
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Publication number: 20110154120Abstract: An apparatus for integratedly managing static analysis tools includes: a tool configuration module receiving initial configuration information in an integrated configuration format for an analysis of static analysis tools from a user, converting the initial configuration information in the integrated configuration format into initial configuration information in an initial configuration format of the static analysis tools, and transmitting the same; a result output module receiving analysis results from the static analysis tools, converting the received analysis results into a common analysis result format, and outputting the same; an analysis configuration module receiving analysis configuration information from the user, converting the received analysis configuration information into analysis configuration information in an analysis configuration format of the static analysis tools, and transmitting the same; and an execution management module performing one or more of functions such as management of the anType: ApplicationFiled: December 16, 2010Publication date: June 23, 2011Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Tae Ho Kim, Ik Soon Kim, Chae Deok Lim, Dong Sun Lim