Abstract: An electrostatic discharge (ESD) protection device (41, 51, 61, 71, 81) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, one or more serially coupled resistor triggered ESD clamp stages (41, 41?, 41?; 71, 71?, 71?), each stage (41, 41?, 41?; 71, 71?, 71?) comprising first (T1, T1?, T1?, etc.) and second transistors (T2, T2?, T2?? etc.) having a common collector (52, 52?, 52?) and first (26, 26?, 26?) and second (36, 36?, 36?) emitters providing terminals (32, 42; 32?, 42?; 32?, 42?) of each clamp stage (41, 41?, 41?; 71, 71?, 71. A first emitter (25) of the first stage (41, 71) couples to the common terminal (23) and a second emitter (42?) of the last stage (41?, 71?) couples to the I/O terminals (22). Zener diode triggers are not used. Integrated external ESD trigger resistors (29, 29?, 29?; 39, 39?, 39?) (e.g.

Abstract: An electrostatic discharge protection structure includes a first vertical bipolar junction transistor; a second vertical bipolar junction transistor, wherein the second vertical bipolar junction transistor has a common collector with the first vertical bipolar junction transistor, and the common collector has a first conductivity; a horizontal bipolar junction transistor wherein the collector of the horizontal bipolar junction transistor has a second conductivity that is a different conductivity than the first conductivity, and the base of the horizontal bipolar junction transistor is electrically coupled to the common collector of the first vertical bipolar junction transistor and the second vertical bipolar junction transistor; a first avalanche diode electrically coupled to the base and the collector of the first vertical bipolar junction transistor; and a second avalanche diode electrically coupled to the base and the collector of the second vertical bipolar junction transistor.

Abstract: An electrostatic discharge (ESD) protection device (61, 71), coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, multiple serially coupled ESD clamp stages (41, 41?), each stage (41, 41?) comprising an interior node (52, 52?) and first (32, 32?) and second terminal (42, 42?) nodes wherein the first terminal node (42) of the first clamp stage (41) is coupled to the common terminal (23) and the second terminal node (42?) of the last clamp stages (41?) is coupled to the I/O terminals (22). A resistance-capacitance ladder (60) is provided in parallel with some of the clamp stages (41, 41?), with a resistance (R1, R2, R3 etc.) coupled to each of the nodes (32, 52, 65 (42; 32?)) of one of the ESD clamp stages (41, 41?) by first terminals thereof and capacitors (C1, C2, etc.) are coupled between second terminals of the resistances (R1, R2, R3 etc.).