Patents by Inventor Chai-Wei Chang

Chai-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11854825
    Abstract: A method of forming a semiconductor device includes forming a dummy gate over a substrate, forming dielectric materials over a top surface and sidewalls of the dummy gate, and replacing the dummy gate with a gate structure. The dummy gate has a first width located a first distance away from the substrate, a second width located a second distance away from the substrate, and a third width located a third distance away from the substrate. The second distance is less than the first distance. The second width is less than the first width. The third distance is less than the second distance. The third width is greater than the second width.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Bo-Feng Young, Chia-Yang Liao
  • Publication number: 20230395689
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Application
    Filed: July 25, 2023
    Publication date: December 7, 2023
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 11764280
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20230119022
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 11532748
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20220375795
    Abstract: A semiconductor device structure is provided. The device includes a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The includes a gate material layer in the trench. The gate material has a topmost surface that is highly planar.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 24, 2022
    Inventors: Chai-Wei Chang, Po-Chi Wu, Wen-Han Fang
  • Publication number: 20220359726
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Po-Chi Wu, Chai-Wei Chang, Kuo-Hui Chang, Yi-Cheng Chao
  • Patent number: 11469145
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chai-Wei Chang, Po-Chi Wu, Wen-Han Fang
  • Patent number: 11444176
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Kuo-Hui Chang, Yi-Cheng Chao
  • Publication number: 20220246441
    Abstract: A method of forming a semiconductor device includes forming a dummy gate over a substrate, forming dielectric materials over a top surface and sidewalls of the dummy gate, and replacing the dummy gate with a gate structure. The dummy gate has a first width located a first distance away from the substrate, a second width located a second distance away from the substrate, and a third width located a third distance away from the substrate. The second distance is less than the first distance. The second width is less than the first width. The third distance is less than the second distance. The third width is greater than the second width.
    Type: Application
    Filed: April 18, 2022
    Publication date: August 4, 2022
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Bo-Feng Young, Chia-Yang Liao
  • Patent number: 11309189
    Abstract: A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Chia-Yang Liao, Bo-Feng Young
  • Patent number: 11271089
    Abstract: Methods for forming the semiconductor structure are provided. The method includes forming a fin structure and forming a gate dielectric layer across the fin structure. The method includes forming a work function metal layer over the gate dielectric layer and forming a gate electrode layer over the work function metal layer. The method further includes etching the work function metal layer to form a gap and etching the gate dielectric layer to enlarge the gap. The method further includes etching the gate electrode layer from the enlarged gap and forming a dielectric layer covering the gate dielectric layer, the work function metal layer, and the gate electrode layer. In addition, the dielectric layer includes a first portion, a second portion, and a third portion, and the first portion is thicker than the second portion, and the second portion is thicker than the third portion.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chai-Wei Chang, Che-Cheng Chang, Po-Chi Wu, Yi-Cheng Chao
  • Patent number: 11139295
    Abstract: A FinFET device structure is provided. The FinFET device structure includes an isolation structure formed over a substrate and a fin structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure, and the first gate structure has a first width in a direction parallel to the fin structure, the second gate structure has a second width in a direction parallel to the fin structure, and the first width is smaller than the second width. The first gate structure includes a first work function layer having a first height. The second gate structure includes a second work function layer having a second height and a gap between the first height and the second height is in a range from about 1 nm to about 6 nm.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chai-Wei Chang, Po-Chi Wu, Yi-Cheng Chao, Che-Cheng Chang
  • Patent number: 11133400
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Kuo-Hui Chang, Yi-Cheng Chao
  • Publication number: 20210013338
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 10854519
    Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure, the virtual surface is formed between the upper portion and the lower portion, and the lower portion has a tapered width which is gradually tapered from the virtual interface to a bottom surface of the lower portion.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Bo-Feng Young, Yi-Jen Chen
  • Publication number: 20200357655
    Abstract: A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.
    Type: Application
    Filed: July 30, 2020
    Publication date: November 12, 2020
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Chia-Yang Liao, Bo-Feng Young
  • Patent number: 10790394
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 10741408
    Abstract: A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Chia-Yang Liao, Bo-Feng Young
  • Patent number: 10714587
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao