Abstract: A method for packaging a semiconductor device includes following steps. First, a first substrate including at least one first pattern is provided. At least one semiconductor device is disposed on the surface of the first substrate. Next, a spacer with at least one aperture and at least one through hole is provided. Then, the first pattern is aimed at the through hole to connect the first substrate and the spacer, so that the semiconductor device is positioned correspondingly to the aperture. Afterwards, a second substrate including at least one second pattern is provided. Thereon, the second pattern is aimed at the through hole, so that the second substrate is connected to the spacer correspondingly.

Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit defining a cut-out portion disposed adjacent to a periphery of the substrate unit; (2) a grounding element disposed in the cut-out portion and at least partially extending between an upper surface and a lower surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body. The EMI shield is electrically connected to a connection surface of the grounding element, such that the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit defining a cut-out portion disposed adjacent to a periphery of the substrate unit; (2) a grounding element disposed in the cut-out portion and at least partially extending between an upper surface and a lower surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body. The EMI shield is electrically connected to a connection surface of the grounding element, such that the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Abstract: A wafer-level chip package process is provided. First, a transparent substrate having a chip sealing layer and a transparent layer is provided. Then, the chip sealing layer is cut to form a first groove of a predetermined depth, and an adhesive is formed on the chip sealing layer. Next, a wafer having a back surface and an active surface is provided, and the transparent substrate is disposed on the active surface of the wafer, wherein the chip sealing layer is adhered to the active surface by the adhesive. Next, the transparent layer is cut to form a second groove corresponding to the first groove. Next, the back surface of the wafer is cut to form a third groove corresponding to the first groove. After that, the wafer and the transparent substrate are singulated to form a plurality of chip package structures.

Abstract: A wafer dicing process for optical electronic packing is provided. The process includes: providing a first wafer (glass wafer) and a second wafer (interposer wafer); etching the second wafer to form a reference flat coordinate; laminating the first wafer on the second wafer; providing a third wafer (CMOS wafer); laminating the third wafer under the second wafer; cutting the first wafer by a first dicing saw according to the reference flat coordinate; and cutting the third wafer by a second dicing saw to form a first reference axis and a second reference axis perpendicular to each other and to establish a backside dicing reference coordinate. The process not only can reduce wearing loss of the dicing saws but also ensure to form high quality cutting edges and a precise backside dicing reference coordinate.

Abstract: A wafer-level chip package process is provided. First, a transparent substrate having a chip sealing layer and a transparent layer is provided. Then, the chip sealing layer is cut to form a first groove of a predetermined depth, and an adhesive is formed on the chip sealing layer. Next, a wafer having a back surface and an active surface is provided, and the transparent substrate is disposed on the active surface of the wafer, wherein the chip sealing layer is adhered to the active surface by the adhesive. Next, the transparent layer is cut to form a second groove corresponding to the first groove. Next, the back surface of the wafer is cut to form a third groove corresponding to the first groove. After that, the wafer and the transparent substrate are singulated to form a plurality of chip package structures.

Abstract: A method for packaging an semiconductor device includes following steps. First, a first substrate including at least one first pattern is provided. At least one semiconductor device is disposed on the surface of the first substrate. Next, a spacer with at least one aperture and at least one through hole is provided. Then, the first pattern is aimed at the through hole to connect the first substrate and the spacer, so that the semiconductor device is positioned correspondingly to the aperture. Afterwards, a second substrate including at least one second pattern is provided. Thereon, the second pattern is aimed at the through hole, so that the second substrate is connected to the spacer correspondingly.

Abstract: An optoelectronic package with a wire-protection lid is provided. An active surface of a silicon die includes a light working area. The silicon die is disposed on a substrate and electrically connected to the substrate through a plurality of bonding wires. A glass is disposed on the active surface of the silicon die. A silicon base lid with an opening is located above the substrate and connected to the glass by anodic bonding to mask the bonding wires. In addition, the opening of the silicon base lid is aligned with the light working area of the silicon die.

Abstract: A wafer dicing process for optical electronic packing is provided. The process includes: providing a first wafer (glass wafer) and a second wafer (interposer wafer); etching the second wafer to form a reference plane coordinate; laminating the first wafer on the second wafer, providing a third wafer (CMOS wafer); laminating the third wafer under the second wafer, cutting the first wafer by a first dicing saw according to the reference plane coordinate, dicing the third wafer by a second dicing saw to form a first reference axis and a second reference axis perpendicular with each other and to establish a backside dicing reference coordinate. The process not only can reduce wearing loss of the dicing saws but also ensure to form high quality cutting edges and a precise backside dicing reference coordinate.

Abstract: An optoelectronic package with a wire-protection lid is provided. An active surface of a silicon die includes a light working area. The silicon die is disposed on a substrate and electrically connected to the substrate through a plurality of bonding wires. A glass is disposed on the active surface of the silicon die. A silicon base lid with an opening is located above the substrate and connected to the glass by anodic bonding to mask the bonding wires. In addition, the opening of the silicon base lid is aligned with the light working area of the silicon die.