Abstract: Aspects include performing integrated circuit design. A processor identifies a child block of an integrated circuit for placement of a buffer-bay to insert a buffer in a portion of the integrated circuit reserved for the child block. The buffer-bay is divided into a plurality of buffer-bay segments. Parent-level routing information and one or more boundary conditions are analyzed to determine a plurality of placement options for the buffer-bay segments. A best possible placement is selected from the plurality of placement options for the buffer-bay segments as a planned buffer-bay layout. A routing of the integrated circuit is performed based on the planned buffer-bay layout.

Abstract: Aspects include performing integrated circuit design. A processor identifies a child block of an integrated circuit for placement of a buffer-bay to insert a buffer in a portion of the integrated circuit reserved for the child block. The buffer-bay is divided into a plurality of buffer-bay segments. Parent-level routing information and one or more boundary conditions are analyzed to determine a plurality of placement options for the buffer-bay segments. A best possible placement is selected from the plurality of placement options for the buffer-bay segments as a planned buffer-bay layout. A routing of the integrated circuit is performed based on the planned buffer-bay layout.

Abstract: As disclosed herein, a method, executed by a computer, for integrated circuit timing variability reduction includes loading a netlist that corresponds to a chip design, where the chip design includes one or more circuits and a plurality of post-fill features, traversing a portion of the netlist corresponding to a circuit, determining a post-fill environment for the circuit from a plurality of post-fill features, and modeling a timing variance for the circuit based on the post-fill environment. The method may also include changing one or more post-fill features to achieve a targeted delay. The method may include generating a report of circuit timing and timing variances. One or more circuits can be concurrently traversed. The timing variance can be modeled with the use of a scaling factor for a standard timing variance. A computer system and computer program product corresponding to the method are also disclosed herein.