Patents by Inventor Chaitanya Palusa
Chaitanya Palusa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10084591Abstract: Embodiments enable built-in sinusoidal jitter injection, for example, in a serializer/deserializer (SERDES) circuit. For example, embodiments can receive a tracking profile that corresponds to a predetermined sinusoidal jitter (SJ) profile and a predetermined phase interpolator (PI) profile. A shift determination can be made for each of a plurality of insertion times according to the tracking profile, the shift determination indicating whether to adjust phase interpolation of the SERDES circuit. At each of the plurality of insertion times, a phase adjustment signal can be generated as a function of the shift determination. For example, the phase adjustment signal can indicate a control code for a phase interpolator coupled to a clock generator of the SERDES, and the signal can be output to the phase interpolator. Some implementations adjust the phase interpolator in response to the phase adjustment signal, such that the phase interpolator injects SJ that substantially tracks the SJ profile.Type: GrantFiled: March 21, 2017Date of Patent: September 25, 2018Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Chaitanya Palusa, Dawei Huang, Jiangyuan Li, Pradeep Nagarajan
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Patent number: 9917607Abstract: Embodiments include systems and methods for baseline wander correction gain adaptation in receiver circuits. Some embodiments operate in context of an alternating current coupled transceiver communicating data signals over a high-speed transmission channel, such that the receiver system includes an AC-coupled data input and a feedback loop with a data slicer and an error slicer. A baseline wander correction (BWC) circuit can be part of the feedback loop and can generate a feedback signal corresponding to low-pass-filtered bits data from the data slicer output and having a gain generated according to pattern-filtered error data from the error slicer output. For example, gain adaptation is performed according to error information corresponding to a detected relatively high-frequency data pattern following a long low-frequency pattern.Type: GrantFiled: March 3, 2017Date of Patent: March 13, 2018Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Xun Zhang, Dawei Huang, Jianghui Su, Chaitanya Palusa
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Patent number: 9385893Abstract: Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.Type: GrantFiled: February 10, 2014Date of Patent: July 5, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Chaitanya Palusa, Tomasz Prokop, Hiep T. Pham, Volodymyr Shvydun, Adam B. Healey
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Patent number: 9304535Abstract: Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.Type: GrantFiled: March 21, 2014Date of Patent: April 5, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Volodymyr Shvydun, Adam B. Healey, Chaitanya Palusa, Hiep T. Pham
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Patent number: 9215106Abstract: A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.Type: GrantFiled: March 21, 2014Date of Patent: December 15, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Chaitanya Palusa, Adam B. Healey, Hiep T. Pham, Volodymyr Shvydun
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Publication number: 20150256363Abstract: An N-way parallel, unrolled decision feedback equalizer for a SerDes receiver can convert between four-tap PAM-2 and two-tap PAM-4 mode, maximizing hardware through the use of mode control multiplexers. Each of N interleaved parallel branches includes an ISI correction stage for generating a partial result approximating intersymbol interference and comparing the partial result to a threshold, a carry look-ahead stage for generating a second partial result based in part on previously generated partial results, and a decision feedback stage for generating a final decision based on previous branches. Mode control multiplexers can select from PAM-2 and PAM-4 operating modes, PAM-2 and MAP-4 inputs at various stages, or from single-bit PAM-2 and two-bit PAM-4 outputs. ISI correction can additionally be reformulated to incorporate comparing raw input symbols to a combination of approximated ISI and a threshold.Type: ApplicationFiled: March 27, 2014Publication date: September 10, 2015Applicant: LSI CorporationInventors: Volodymyr Shvydun, Adam B. Healey, Chaitanya Palusa
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Patent number: 9130797Abstract: An interleaved track-and-hold front-end with multiphase clocks computes and propagates unrolled decision feedback equalization results along a pipeline with the final outputs selected from one of the interleaved previous output bits with a multiplexer operating over multiple unit intervals instead of one unit interval. An n-way interleaved serializer/deserializer utilizes an n unit interval multiplexer or n one unit interval multiplexers. Pipelined decision feedback equalization allows multiple, slower multiplexers.Type: GrantFiled: May 1, 2014Date of Patent: September 8, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Chaitanya Palusa, Volodymyr Shvydun, Hiep T. Pham, Adam B. Healey
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Publication number: 20150234423Abstract: Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.Type: ApplicationFiled: March 21, 2014Publication date: August 20, 2015Applicant: LSI CorporationInventors: Volodymyr Shvydun, Adam B. Healey, Chaitanya Palusa, Hiep T. Pham
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Publication number: 20150236875Abstract: A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.Type: ApplicationFiled: March 21, 2014Publication date: August 20, 2015Applicant: LSI CorporationInventors: Chaitanya Palusa, Adam B. Healey, Hiep T. Pham, Volodymyr Shvydun
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Publication number: 20150207648Abstract: Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.Type: ApplicationFiled: February 10, 2014Publication date: July 23, 2015Applicant: LSI CorporationInventors: Chaitanya Palusa, Tomasz Prokop, Hiep T. Pham, Volodymyr Shvydun, Adam B. Healey
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Patent number: 9077574Abstract: A SerDes receiver device can receive binary signals via wireline channel such that information recovery is primarily or entirely performed via DSP algorithms in the digital domain includes an analog to digital converter, adaptation and calibration blocks, and a sequential n-way parallel equalization data path. The data path provides preliminary equalization of digital input symbols through a feed forward equalizer block followed by a decision feedback equalizer block, to which a k-slice decision feed forward equalizer block is appended for generating equalized hard decision outputs. The decision feed forward equalizer block may include a concatenation of cascading DFFE slices to improve the performance of the data path.Type: GrantFiled: March 27, 2014Date of Patent: July 7, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Adam B. Healey, Chaitanya Palusa, Tomasz Prokop, Volodymyr Shvydun
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Patent number: 9036729Abstract: A repeater includes a clock-and-data recovery element and a phase interpolator to extract an embedded clock frequency from a data stream. The phase interpolator determine a frequency offset and sends such offset as phase interpolator codes to a filter and scaler. The filtered, scaled phase interpolator codes are used to produce a reference clock frequency for retransmission.Type: GrantFiled: April 29, 2013Date of Patent: May 19, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Hiep Pham, Chaitanya Palusa, Tomasz Prokop, Adam Healey
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Patent number: 8976854Abstract: A reconfigurable P-way parallel N-tap feed forward equalizer includes an adaptive filter configured to generate a series of coefficients (taps) and an input register for storing input symbols. A variable cursor position defined by a parameter corresponding to a position in the input register selects a set of pre-cursor and post-cursor taps for dynamic ISI correction of a like set of pre-cursor and post-cursor symbols. Multiplier banks generate partial result symbols by applying the taps to the set of input symbols, and a set of combiners or adder banks generate equalized output symbols from the partial result symbols. Two multiplexers adjust input symbols and coefficients according to the parameter, and a controller allows selection of an optimal parameter, and thus an optimal variable cursor position. The coefficient corresponding to the parameter may additionally be preset to save storage space.Type: GrantFiled: February 28, 2014Date of Patent: March 10, 2015Assignee: LSI CorporationInventors: Adam B. Healey, Tomasz Prokop, Volodymyr Shvydun, Chaitanya Palusa
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Publication number: 20140233668Abstract: A repeater includes a clock-and-data recovery element and a phase interpolator to extract an embedded clock frequency from a data stream. The phase interpolator determine a frequency offset and sends such offset as phase interpolator codes to a filter and scaler. The filtered, scaled phase interpolator codes are used to produce a reference clock frequency for retransmission.Type: ApplicationFiled: April 29, 2013Publication date: August 21, 2014Applicant: LSI CorporationInventors: Hiep Pham, Chaitanya Palusa, Tomasz Prokop, Adam Healey
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Patent number: 8804889Abstract: A receiver derives the desired data sampling clock phase by averaging the phase information of transitions before and after a data eye. The average of the phase information reduces data clock phase error due to variations in the phases of transitions in received data signals depending on the polarity and positions of the transitions.Type: GrantFiled: January 10, 2013Date of Patent: August 12, 2014Assignee: LSI CorporationInventors: Chaitanya Palusa, Tomasz Prokop
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Patent number: 8787439Abstract: In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.Type: GrantFiled: March 13, 2012Date of Patent: July 22, 2014Assignee: LSI CorporationInventors: Chaitanya Palusa, Tomasz Prokop, Adam B. Healey, Ye Liu
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Publication number: 20140192935Abstract: A receiver derives the desired data sampling clock phase by averaging the phase information of transitions before and after a data eye. The average of the phase information reduces data clock phase error due to variations in the phases of transitions in received data signals depending on the polarity and positions of the transitions.Type: ApplicationFiled: January 10, 2013Publication date: July 10, 2014Applicant: LSI CORPORATIONInventors: Chaitanya Palusa, Tomasz Prokop
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Patent number: 8582635Abstract: In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.Type: GrantFiled: March 2, 2012Date of Patent: November 12, 2013Assignee: LSI CorporationInventors: Tomasz Prokop, Chaitanya Palusa
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Publication number: 20130243066Abstract: In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.Type: ApplicationFiled: March 13, 2012Publication date: September 19, 2013Inventors: Chaitanya Palusa, Tomasz Prokop, Adam B. Healey, Ye Liu
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Publication number: 20130230092Abstract: In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.Type: ApplicationFiled: March 2, 2012Publication date: September 5, 2013Inventors: Tomasz Prokop, Chaitanya Palusa