Patents by Inventor Chaithanya Velampalli

Chaithanya Velampalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus to reduce delays in channel estimation
    Patent number: 10567200
    Abstract: A signal processor and method of signal processing to reduce delays in channel estimation is described. In the method, the following operations are performed: receiving a signal at a signal processor (200); estimating a first channel from the received signal with a one-dimensional, 1D, frequency filter (304) in a frequency domain to generate an interim output; decoding said interim output (406) to generate decoded interim output; estimating (414,418) at least a second channel from the decoded interim output with a two-dimensional, 2D, filter (100) to produce a final output (420).
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: February 18, 2020
    Assignee: NXP B.V.
    Inventors: Naveen Jacob, Chaithanya Velampalli
  • METHOD AND APPARATUS TO REDUCE DELAYS IN CHANNEL ESTIMATION
    Publication number: 20190268182
    Abstract: A signal processor and method of signal processing to reduce delays in channel estimation is described. In the method, the following operations are performed: receiving a signal at a signal processor (200); estimating a first channel from the received signal with a one-dimensional, 1D, frequency filter (304) in a frequency domain to generate an interim output; decoding said interim output (406) to generate decoded interim output; estimating (414,418) at least a second channel from the decoded interim output with a two-dimensional, 2D, filter (100) to produce a final output (420).
    Type: Application
    Filed: February 15, 2019
    Publication date: August 29, 2019
    Inventors: Naveen Jacob, Chaithanya Velampalli