Patents by Inventor Chaiyasit Manovit
Chaiyasit Manovit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8898401Abstract: Methods and apparatuses are disclosed that allow for improved speculation success in execute ahead microprocessors. In some embodiments, the method may include speculatively executing a first thread of a program code while a second thread of the program code is executing, determining if a load request is serviceable from a cache line within a cache, and in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line. The method also may include determining whether the cache line associated with the first indicator bit has been evicted, and in the event that the cache line is evicted, allowing speculative execution of the first thread to continue.Type: GrantFiled: November 7, 2008Date of Patent: November 25, 2014Assignee: Oracle America, Inc.Inventors: Chaiyasit Manovit, Paul Nicholas Loewenstein
-
Patent number: 8423935Abstract: One embodiment of a method for verifying functional equivalency between a design of an integrated circuit and a corresponding clock-gated design utilizing output-based clock gating includes selecting a first one of a first plurality of internal state elements in the design and a corresponding first one of a second plurality of internal state elements in the clock-gated design, wherein an input to the first one of the first plurality of internal state elements serves as a first comparison point and an input to the corresponding first one of the second plurality of internal state elements serves as a second comparison point, and the design is to be compared against the clock-gated design at the first comparison point and the second comparison point and generating a test bench that identifies the first comparison point and the second comparison point as a set of comparison points.Type: GrantFiled: February 25, 2011Date of Patent: April 16, 2013Assignee: Xilinx, Inc.Inventors: Chaiyasit Manovit, Sridhar Narayanan, Wanlin Cao, Sridhar Subramanian, Alok Kuchlous
-
Patent number: 8219946Abstract: In one embodiment, a method is provided for generating clock gating circuitry for a circuit design model. A Boolean expression of path sensitization is determined for each gate element in the netlist of a circuit design. For each gate element, a conjunction of the Boolean expression of the path sensitization and a Boolean expression of a disjunction of the observability conditions of one or more subsequent gates is determined to produce an intermediate Boolean expression. Intermediate Boolean expressions are backward retimed to produce the respective Boolean expression of the observability conditions of the each gate element. Clock gating circuits that implement the respective Boolean expression of the observability conditions of one or more of the plurality of interconnected gate elements are generated and incorporated into the circuit design model.Type: GrantFiled: July 13, 2010Date of Patent: July 10, 2012Assignee: Xilinx, Inc.Inventors: Chaiyasit Manovit, Wanlin Cao, Sridhar Narayanan, Sridhar Subramanian
-
Patent number: 8099703Abstract: Embodiments of the present invention provide methods and systems for verifying functional equivalence of a power optimized design and its original, unoptimized design (referred to as the golden design) using combinational equivalency checking. Due to some inherent limitations which make combinational equivalency checkers unable to prove equivalency of the two designs in a single step, a series of intermediate design transformations is introduced. These transformations are dependent on the techniques used in generating the power optimized design from the golden design, and may be generically described in a transformation language that provides the necessary constructs to specify an entire set of valid structural modifications.Type: GrantFiled: December 1, 2008Date of Patent: January 17, 2012Assignee: Xilinx, Inc.Inventors: Chaiyasit Manovit, Sridhar Narayanan, Sridhar Subramanian
-
Patent number: 7814378Abstract: A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model. Further, a backtracking search may be performed to find a valid ordering if such ordering exists or show that none exists and, hence, confirm whether or not the results comply with the given memory consistency model.Type: GrantFiled: May 18, 2007Date of Patent: October 12, 2010Assignee: Oracle America, Inc.Inventors: Chaiyasit Manovit, Sudheendra G. Hangal
-
Patent number: 7779393Abstract: A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model.Type: GrantFiled: May 25, 2005Date of Patent: August 17, 2010Assignee: Oracle America, Inc.Inventors: Chaiyasit Manovit, Sudheendra G. Hangal, Robert E. Cypher
-
Patent number: 7746116Abstract: One aspect of the invention relates to a device including a first storage element and a first clock gating element, wherein a data input of the first storage element is coupled to an output of a combinatorial logic (CL) element, wherein the first storage element is clock-gated with the first clock gating element using a first clock enable signal to generate a clock signal for the first storage element, wherein the first clock enable signal is generated to suppress the clock signal in the first clock gating element when each of the at least one data input of the CL element is in a second quiescence inducing condition with respect to the clock signal at the same time as when each of the at least one control input of the CL element is in the first quiescence inducing condition.Type: GrantFiled: January 21, 2009Date of Patent: June 29, 2010Assignee: XILINX, Inc.Inventors: Sridhar Narayanan, Chaiyasit Manovit, Sridhar Subramanian, Gerald Gras
-
Publication number: 20100122038Abstract: Methods and apparatuses are disclosed that allow for improved speculation success in execute ahead microprocessors. In some embodiments, the method may include speculatively executing a first thread of a program code while a second thread of the program code is executing, determining if a load request is serviceable from a cache line within a cache, and in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line. The method also may include determining whether the cache line associated with the first indicator bit has been evicted, and in the event that the cache line is evicted, allowing speculative execution of the first thread to continue.Type: ApplicationFiled: November 7, 2008Publication date: May 13, 2010Applicant: Sun Microsystems, Inc.Inventors: Chaiyasit Manovit, Paul Nicholas Loewenstein
-
Publication number: 20080288834Abstract: A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model. Further, a backtracking search may be performed to find a valid ordering if such ordering exists or show that none exists and, hence, confirm whether or not the results comply with the given memory consistency model.Type: ApplicationFiled: May 18, 2007Publication date: November 20, 2008Inventors: Chaiyasit Manovit, Sudheendra G. Hangal
-
Patent number: 6892286Abstract: A system and method for verifying a memory consistency model for a shared memory multiprocessor computer systems generates random instructions to run on the processors, saves the results of the running of the instructions, and analyzes the results to detect a memory subsystem error if the results fall outside of the space of possible outcomes consistent with the memory consistency model. A precedence relationship of the results is determined by uniquely identifying results of a store location with each result distinct to allow association of a read result value to the instruction that created the read result value. A precedence graph with static, direct and derived edges identifies errors when a cycle is detected that indicates results that are inconsistent with memory consistency model rules.Type: GrantFiled: September 30, 2002Date of Patent: May 10, 2005Assignee: Sun Microsystems, Inc.Inventors: Sudheendra Hangal, Durgam Vahia, Juin-Yeu Lu, Chaiyasit Manovit