Patents by Inventor Chaiyuth Chansungsan

Chaiyuth Chansungsan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7157947
    Abstract: In some embodiments, a circuit includes a reference current source to provide a substantially noise free current signal, and a detector coupled to one or two power supplies. In some embodiments, a method includes receiving a substantially noise free current signal, receiving one or two power supply signals, processing the substantially noise free current signal and the one or two power supply signals to detect a noise signal in the one or two power supply signals, and generating a noise detection signal in response to detection of the noise signal.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventors: Chaiyuth Chansungsan, Keith Self
  • Patent number: 7102404
    Abstract: An improved interpolator includes a replica delay line and an interpolated delay edge generator. The replica delay line provides two replica delay edges to the interpolated delay edge generator. The interpolated delay edge generator selectively generates an interpolated delay edge while maintaining a substantially constant capacitive loading on the two replica delay edges. The replica delay line may comprise a delay cell of four current-starved inverter delay stages or four capacitor-loaded inverter delay stages.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventor: Chaiyuth Chansungsan
  • Publication number: 20050258882
    Abstract: An improved interpolator includes a replica delay line and an interpolated delay edge generator. The replica delay line provides two replica delay edges to the interpolated delay edge generator. The interpolated delay edge generator selectively generates an interpolated delay edge while maintaining a substantially constant capacitive loading on the two replica delay edges. The replica delay line may comprise a delay cell of four current-stared inverter delay stages or four capacitor-loaded inverter delay stages.
    Type: Application
    Filed: June 30, 2005
    Publication date: November 24, 2005
    Inventor: Chaiyuth Chansungsan
  • Publication number: 20050242856
    Abstract: An improved interpolator includes a replica delay line and an interpolated delay edge generator. The replica delay line provides two replica delay edges to the interpolated delay edge generator. The interpolated delay edge generator selectively generates an interpolated delay edge while maintaining a substantially constant capacitive loading on the two replica delay edges. The replica delay line may comprise a delay cell of four current-starved inverter delay stages or four capacitor-loaded inverter delay stages.
    Type: Application
    Filed: June 30, 2005
    Publication date: November 3, 2005
    Inventor: Chaiyuth Chansungsan
  • Publication number: 20050122138
    Abstract: In some embodiments, a circuit includes a reference current source to provide a substantially noise free current signal, and a detector coupled to one or two power supplies. In some embodiments, a method includes receiving a substantially noise free current signal, receiving one or two power supply signals, processing the substantially noise free current signal and the one or two power supply signals to detect a noise signal in the one or two power supply signals, and generating a noise detection signal in response to detection of the noise signal.
    Type: Application
    Filed: December 9, 2003
    Publication date: June 9, 2005
    Inventors: Chaiyuth Chansungsan, Keith Self
  • Publication number: 20040222832
    Abstract: An improved interpolator includes a replica delay line and an interpolated delay edge generator. The replica delay line provides two replica delay edges to the interpolated delay edge generator. The interpolated delay edge generator selectively generates an interpolated delay edge while maintaining a substantially constant capacitive loading on the two replica delay edges. The replica delay line may comprise a delay cell of four current-starved inverter delay stages or four capacitor-loaded inverter delay stages.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 11, 2004
    Inventor: Chaiyuth Chansungsan
  • Patent number: 6744275
    Abstract: Various apparatuses and methods are described that include a variable-impedance matched termination pair coupled to differential signaling bus pair. In an embodiment, the differential signaling bus pair includes a first bus and a second bus. The variable-impedance matched termination pair includes a first variable-impedance component and a second variable-impedance component. The impedance value of each variable-impedance component depends on the voltage level sensed by that variable-impedance component. The first variable-impedance component couples to the first bus. The second variable-impedance component couples to the second bus. The first variable-impedance component is electrically isolated from the second variable-impedance resistor.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: June 1, 2004
    Assignee: Intel Corporation
    Inventor: Chaiyuth Chansungsan
  • Patent number: 6744287
    Abstract: A bi-directional communication system includes a driver capable of controlling a slew rate of transmitted data signals. Impedance matching can be provided to match an impedance of a driver circuit to an impedance of a communication line. The impedance is maintained constant as data is driven from the data driver. The data receiver circuit can adjust a reference voltage in response to simultaneously transmitted data. The slew rate of the receiver circuit trip point is controlled to maintain adequate noise margin during operation. Both the receiver and driver circuits can be controlled using a delay line circuit.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: June 1, 2004
    Assignee: Intel Corporation
    Inventors: Stephen R. Mooney, Joseph T. Kennedy, Chaiyuth Chansungsan, Prantik K. Nag
  • Publication number: 20030146772
    Abstract: Various apparatuses and methods are described that include a variable-impedance matched termination pair coupled to differential signaling bus pair. In an embodiment, the differential signaling bus pair includes a first bus and a second bus. The variable-impedance matched termination pair includes a first variable-impedance component and a second variable-impedance component. The impedance value of each variable-impedance component depends on the voltage level sensed by that variable-impedance component. The first variable-impedance component couples to the first bus. The second variable-impedance component couples to the second bus. The first variable-impedance component is electrically isolated from the second variable-impedance resistor.
    Type: Application
    Filed: February 1, 2002
    Publication date: August 7, 2003
    Inventor: Chaiyuth Chansungsan
  • Publication number: 20020190762
    Abstract: A bi-directional communication system includes a driver capable of controlling a slew rate of transmitted data signals. Impedance matching can be provided to match an impedance of a driver circuit to an impedance of a communication line. The impedance is maintained constant as data is driven from the data driver. The data receiver circuit can adjust a reference voltage in response to simultaneously transmitted data. The slew rate of the receiver circuit trip point is controlled to maintain adequate noise margin during operation. Both the receiver and driver circuits can be controlled using a delay line circuit.
    Type: Application
    Filed: August 21, 2002
    Publication date: December 19, 2002
    Applicant: Intel Corporation
    Inventors: Stephen R. Mooney, Joseph T. Kennedy, Chaiyuth Chansungsan, Prantik K. Nag
  • Patent number: 6452428
    Abstract: A bi-directional communication system includes a driver capable of controlling a slew rate of transmitted data signals. Impedance matching can be provided to match an impedance of a driver circuit to an impedance of a communication line. The impedance is maintained constant as data is driven from the data driver. The data receiver circuit can adjust a reference voltage in response to simultaneously transmitted data. The slew rate of the receiver circuit trip point is controlled to maintain adequate noise margin during operation. Both the receiver and driver circuits can be controlled using a delay line circuit.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: September 17, 2002
    Assignee: Intel Corporation
    Inventors: Stephen R. Mooney, Joseph T. Kennedy, Chaiyuth Chansungsan, Prantik K. Nag