Abstract: A content access device includes an interface module that receives a transport stream and outputs a processed transport stream. An input buffer buffers the received transport stream. A polling processor processes the transport stream based on the at least one key to generate the processed transport stream, wherein the polling processor operates to descramble individual packets of the transport stream in a plurality of polling slots of a polling loop. An output buffer buffers the processed transport stream for output by the interface module.

Abstract: A content access device includes an interface module that receives a transport stream and outputs a processed transport stream. An input buffer buffers the received transport stream. A polling processor processes the transport stream based on the at least one key to generate the processed transport stream, wherein the polling processor operates to descramble individual packets of the transport stream in a plurality of polling slots of a polling loop. An output buffer buffers the processed transport stream for output by the interface module.

Abstract: A spurious-free fractional-N frequency synthesizer circuit is disclosed. The synthesizer circuit includes a multi-phase network circuit operative to provide output signals that are at least a 1/(2n+1)) fractional version of the input signal. The synthesizer circuit includes a phase lock loop (PLL) circuit, with the multi-phase network circuit being coupled to the negative feedback loop of the PLL. The multi-phase network circuit includes a smoothing circuit that removes any jitter present at the output of the PLL.

Abstract: A spurious-free fractional-N frequency synthesizer circuit is disclosed. The synthesizer circuit includes a multi-phase network circuit operative to provide output signals that are at least a 1/(2n+1)) fractional version of the input signal. The synthesizer circuit includes a phase lock loop (PLL) circuit, with the multi-phase network circuit being coupled to the negative feedback loop of the PLL. The multi-phase network circuit includes a smoothing circuit that removes any jitter present at the output of the PLL.

Abstract: A method and apparatus for providing serial transmission of a parallel input is accomplished by a parallel input serial output transmitter that includes a shift register operably coupled to receive a parallel input and to provide data serially to a gating circuit. The gating circuit, based on the state of the data it receives, generates a drive signal which causes a switching circuit to route current from first and second current sources to a third current source over different paths to produce a serial output. A bias circuit is coupled to the switching circuit to bias the serial output to a desired level.

Abstract: A method and apparatus for providing serial transmission of a parallel input is accomplished by a parallel input serial output transmitter that includes a shift register operably coupled to receive a parallel input and to provide data serially to a gating circuit. The gating circuit, based on the state of the data it receives, generates a drive signal which causes a switching circuit to route current from first and second current sources to a third current source over different paths to produce a serial output. A bias circuit is coupled to the switching circuit to bias the serial output to a desired level.

Abstract: A method and apparatus for providing serial transmission of a parallel input is accomplished by a parallel input serial output transmitter that includes a shift register operably coupled to receive a parallel input and to provide data serially to a gating circuit. The gating circuit, based on the state of the data it receives, generates a drive signal which causes a switching circuit to route current from a first current source to a second current source over different paths to produce a serial output. A bias circuit is coupled to the switching circuit to bias the serial output to a desired level.