Abstract: A cryptosystem processor includes a twiddle factor memory, a SRDGT BFU, and a SPN. The twiddle factor memory has ZETA ports. The at least one SRDGT BFU has six input ports and four output ports and switchable among operation in DGT/IDGT/CWM mode, in which two of the input ports electrically communicate with the ZETA ports, respectively. The SRDGT BFU is configured to read and write two data points when working under the DGT/IDGT mode and is configured to read and write four data points when working under the CWM mode. The SPN electrically communicates with the SRDGT BFU and has at least one dual-port BRAM serving as memory cache configured to store polynomial, in which the SPN is configured to support the required number of data points reading or writing per cycle in the DGT/IDGT/CWM mode.

Abstract: A processor for a cryptosystem. The processor comprises a hybrid processor architecture including a hardware processor, a software processor and an interconnection interface arranged to exchange data between the hardware processor and the software processor; wherein the hardware processor comprises a plurality of hardware accelerator modules arranged to perform computational tasks including at least one of number theoretic transforms (NTT) computation, arithmetic operations which are more time-consuming when being performed instead by the software-processor.

Abstract: A processor for a cryptosystem. The processor comprises a hybrid processor architecture including a hardware processor, a software processor and an interconnection interface arranged to exchange data between the hardware processor and the software processor; wherein the hardware processor comprises a plurality of hardware accelerator modules arranged to perform computational tasks including at least one of number theoretic transforms (NTT) computation, arithmetic operations which are more time-consuming when being performed instead by the software-processor.

Abstract: The present invention provides a system for implementing a logistic regression classification mechanism to measure and assess a depth of anesthesia of an animal subject based on electroencephalography (EEG), which includes a signal pre-processor, an epoch generator, a feature extractor, a classifier, and a predictor. Related method of how to pre-process the raw data of EEG signal, epoch generation thereof, feature extraction from each epoch, classification based on extracted features, and prediction of different states of the animal subject based on a prediction decision mechanism is also provided. Classification accuracy of the present invention for 1-second and 10% overlapping epochs is about 94% with an average total system delay of about 12 ?s and low on-chip power consumption. The present system is entirely optimized, which leads to a 100% accurate channel prediction after a 7-second run-time on average.

Abstract: The present invention provides a hardware-friendly framework for implementing a point-of-care diagnosis hardware tool for practical end-user convenience, power saving and resource utilization. The hardware tool is non-invasive and comfortable for the patient, as a primary means of differential diagnosis between two neuromuscular diseases such as neuropathy and myopathy. The provided hard-ware tool comprises a feature extractor configured to receive electrodiagnostic signals (preferably EMG signals) of a patient and extract one or more features from the collected signals; and a classifier configured to receive the extracted features and classify a neuromuscular disease for the patient based on the extracted features. The classifier is a single layer machine-learning perceptron trained with datasets consisted of electrodiagnostic signals of patients to perform a linearly separable binary classification.