Patents by Inventor CHAKKRIT SUPAVASUTHI

CHAKKRIT SUPAVASUTHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEMS AND METHODS FOR CORRECTING READ/WRITE OVERLAY ERRORS IN THE MANUFACTURE OF MAGNETIC TRANSDUCERS FOR STORAGE DRIVES
    Publication number: 20160346898
    Abstract: Systems and methods for correcting read/write overlay errors in the manufacture of magnetic transducers for storage drives are provided. One such system includes a twisting tool configured to receive and secure a row bar having an elongated rectangular block shape and including a plurality of magnetic transducers spaced apart along a length of the row bar, and where the twisting tool is configured to twist the row bar at a plurality of areas along the length of the row bar.
    Type: Application
    Filed: August 11, 2016
    Publication date: December 1, 2016
    Inventors: MARK D. MORAVEC, CHAKKRIT SUPAVASUTHI, THEERA YAEMGLIN
  • Systems and methods for correcting read/write overlay errors in the manufacture of magnetic transducers for storage drives
    Patent number: 9427842
    Abstract: Systems and methods for correcting read/write overlay errors in the manufacture of magnetic transducers for storage drives are provided. One such system includes a twisting tool configured to receive and secure a row bar having an elongated rectangular block shape and including a plurality of magnetic transducers spaced apart along a length of the row bar, and where the twisting tool is configured to twist the row bar at a plurality of areas along the length of the row bar.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: August 30, 2016
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mark D. Moravec, Chakkrit Supavasuthi, Theera Yaemglin
  • Systems and methods for correcting slider parallelism error using compensation lapping
    Patent number: 9343084
    Abstract: Systems and methods for correcting slider parallelism error using compensation lapping are described. One such system includes a lapping support including at least one mounting surface having a preselected mounting angle such that a line normal to the at least one mounting surface is not parallel to a centerline of the lapping support, a rowbar including a plurality of magnetic transducers spaced apart along a length of the rowbar, and a lapping plate configured to lap the rowbar, where the rowbar is mounted to the at least one mounting surface, and where the rowbar is configured to be brought into contact with the lapping plate.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: May 17, 2016
    Assignee: Western Digital Technologies, Inc.
    Inventors: Theera Yaemglin, Chakkrit Supavasuthi
  • SYSTEMS AND METHODS FOR CORRECTING SLIDER PARALLELISM ERROR USING COMPENSATION LAPPING
    Publication number: 20130244541
    Abstract: Systems and methods for correcting slider parallelism error using compensation lapping are described. One such system includes a lapping support including at least one mounting surface having a preselected mounting angle such that a line normal to the at least one mounting surface is not parallel to a centerline of the lapping support, a rowbar including a plurality of magnetic transducers spaced apart along a length of the rowbar, and a lapping plate configured to lap the rowbar, where the rowbar is mounted to the at least one mounting surface, and where the rowbar is configured to be brought into contact with the lapping plate.
    Type: Application
    Filed: March 14, 2012
    Publication date: September 19, 2013
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: THEERA YAEMGLIN, CHAKKRIT SUPAVASUTHI