Patents by Inventor Chakravarthy Kosaraju
Chakravarthy Kosaraju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7383468Abstract: The invention relates to the design of highly reliable microprocessors and more specifically to the use of a dedicated state machine that periodically checks the validity of critical processor resources. In an embodiment of the present invention, an apparatus to detect errors in information stored in a processor resource includes an error detection component, which is configured to control the detection of errors in the information stored in the processor resource; and a comparison component coupled to the error detection component, which is configured to receive the information from the processor resource and inputs from the detection component. The comparison component is further configured to determine if the information is valid, and to output a signal to replace the information if the information if invalid.Type: GrantFiled: August 6, 2003Date of Patent: June 3, 2008Assignee: Intel CorporationInventors: Nhon T. Quach, John H. Crawford, Chakravarthy Kosaraju, Venkatesh Nagapudi
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Patent number: 7315920Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.Type: GrantFiled: January 4, 2005Date of Patent: January 1, 2008Assignee: Intel CorporationInventors: Nhon Quach, John Crawford, Greg S. Mathews, Edward Grochowski, Chakravarthy Kosaraju
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Patent number: 7133957Abstract: The invention generally relates to a method, apparatus, and system to change one or more communication pathways in a processor without changing a physical component layout in the processor. For example, in an embodiment, the invention generally relates to a routing agent to change one or more communication pathways in a processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to the following method. The method comprises sending a control signal to one or more components within a processor to change one or more communication pathways in the processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to a method of changing the bandwidth between a processor and a device exterior to the processor without changing the physical component layout in the processor.Type: GrantFiled: August 13, 2004Date of Patent: November 7, 2006Assignee: Intel CorporationInventor: Chakravarthy Kosaraju
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Patent number: 6907490Abstract: The invention generally relates to a method, apparatus, and system to change one or more communication pathways in a processor without changing a physical component layout in the processor. For example, in an embodiment, the invention generally relates to a routing agent to change one or more communication pathways in a processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to the following method. The method comprises sending a control signal to one or more components within a processor to change one or more communication pathways in the processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to a method of changing the bandwidth between a processor and a device exterior to the processor without changing the physical component layout in the processor.Type: GrantFiled: December 13, 2000Date of Patent: June 14, 2005Assignee: Intel CorporationInventor: Chakravarthy Kosaraju
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Patent number: 6904502Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a blind invalidate circuit in high-speed memories. In accordance with an embodiment of the present invention, a tag array memory circuit including a plurality of memory bit circuits coupled together to form an n-bit memory cell; and a blind invalidate circuit coupled to a memory bit circuit in the n-bit memory cell, the blind invalidate circuit to clear a bit in the memory bit circuit, if a primary clear bit line is asserted and a received bit value of a right-adjacent memory bit circuit is zero.Type: GrantFiled: December 23, 2003Date of Patent: June 7, 2005Assignee: Intel CorporationInventors: Nhon Quach, John Crawford, Greg S. Mathews, Edward Grochowski, Chakravarthy Kosaraju
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Publication number: 20050120184Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.Type: ApplicationFiled: January 4, 2005Publication date: June 2, 2005Inventors: Nhon Quach, John Crawford, Greg Mathews, Edward Grochowski, Chakravarthy Kosaraju
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Publication number: 20050021897Abstract: The invention generally relates to a method, apparatus, and system to change one or more communication pathways in a processor without changing a physical component layout in the processor. For example, in an embodiment, the invention generally relates to a routing agent to change one or more communication pathways in a processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to the following method. The method comprises sending a control signal to one or more components within a processor to change one or more communication pathways in the processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to a method of changing the bandwidth between a processor and a device exterior to the processor without changing the physical component layout in the processor.Type: ApplicationFiled: August 13, 2004Publication date: January 27, 2005Inventor: Chakravarthy Kosaraju
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Patent number: 6839814Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.Type: GrantFiled: December 4, 2003Date of Patent: January 4, 2005Assignee: Intel CorporationInventors: Nhon Quach, John Crawford, Greg S. Mathews, Edward Grochowski, Chakravarthy Kosaraju
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Patent number: 6826645Abstract: A method and apparatus in which an arbiter links to a processor having a flexible architecture, and the processor connects to a device through a point to point bus.Type: GrantFiled: December 13, 2000Date of Patent: November 30, 2004Assignee: Intel CorporationInventor: Chakravarthy Kosaraju
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Patent number: 6775746Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.Type: GrantFiled: May 12, 2003Date of Patent: August 10, 2004Assignee: Intel CorporationInventors: Nhon Quach, John Crawford, Greg S. Mathews, Edward Grochowski, Chakravarthy Kosaraju
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Publication number: 20040139280Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a blind invalidate circuit in high-speed memories. In accordance with an embodiment of the present invention, a tag array memory circuit including a plurality of memory bit circuits coupled together to form an n-bit memory cell; and a blind invalidate circuit coupled to a memory bit circuit in the n-bit memory cell, the blind invalidate circuit to clear a bit in the memory bit circuit, if a primary clear bit line is asserted and a received bit value of a right-adjacent memory bit circuit is zero.Type: ApplicationFiled: December 23, 2003Publication date: July 15, 2004Applicant: INTEL CORPORATIONInventors: Nhon T. Quach, John H. Crawford, Gregory S. Mathews, Edward Grochowski, Chakravarthy Kosaraju
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Publication number: 20040078529Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.Type: ApplicationFiled: December 4, 2003Publication date: April 22, 2004Applicant: INTEL CORPORATIONInventors: Nhon T. Quach, John H. Crawford, Greg S. Mathews, Edward Grochowski, Chakravarthy Kosaraju
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Publication number: 20040030959Abstract: The invention relates to the design of highly reliable microprocessors and more specifically to the use of a dedicated state machine that periodically checks the validity of critical processor resources. In an embodiment of the present invention, an apparatus to detect errors in information stored in a processor resource includes an error detection component, which is configured to control the detection of errors in the information stored in the processor resource; and a comparison component coupled to the error detection component, which is configured to receive the information from the processor resource and inputs from the detection component. The comparison component is further configured to determine if the information is valid, and to output a signal to replace the information if the information if invalid.Type: ApplicationFiled: August 6, 2003Publication date: February 12, 2004Applicant: INTEL CORPORATIONInventors: Nhon T. Quach, John H. Crawford, Chakravarthy Kosaraju, Venkatesh Nagapudi
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Patent number: 6675266Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.Type: GrantFiled: December 29, 2000Date of Patent: January 6, 2004Assignee: Intel CorporationInventors: Nhon Quach, John Crawford, Greg S. Mathews, Edward Grochowski, Chakravarthy Kosaraju
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Patent number: 6654909Abstract: The invention relates to the design of highly reliable microprocessors and more specifically to the use of a dedicated state machine that periodically checks the validity of critical processor resources. In an embodiment of the present invention, an apparatus to detect errors in information stored in a processor resource includes an error detection component, which is configured to control the detection of errors in the information stored in the processor resource; and a comparison component coupled to the error detection component, which is configured to receive the information from the processor resource and inputs from the detection component. The comparison component is further configured to determine if the information is valid, and to output a signal to replace the information if the information if invalid.Type: GrantFiled: June 30, 2000Date of Patent: November 25, 2003Assignee: Intel CorporationInventors: Nhon T. Quach, John H. Crawford, Chakravarthy Kosaraju, Venkatesh Nagapudi
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Publication number: 20030196049Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.Type: ApplicationFiled: May 12, 2003Publication date: October 16, 2003Applicant: INTEL CORPORATIONInventors: Nhon Quach, John Crawford, Greg S. Mathews, Edward Grochowski, Chakravarthy Kosaraju
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Patent number: 6510506Abstract: An embodiment of the present invention includes a tag array, a valid vector, and a detector. The tag array stores N tag entries. Each of the N tag entries contains a one-hot tag having K bits. Each of the K bits of the one-hot tag corresponds to a translation look-aside buffer (TLB) entry in a TLB array having K TLB entries. The valid vector stores N valid entries corresponding to the N tag entries. The detector detects an error when a tag entry is read out upon a fetch read operation.Type: GrantFiled: December 28, 2000Date of Patent: January 21, 2003Assignee: Intel CorporationInventors: Venkatesh Nagapudi, Chakravarthy Kosaraju
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Publication number: 20020087808Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.Type: ApplicationFiled: December 29, 2000Publication date: July 4, 2002Inventors: Nhon Quach, John Crawford, Greg S. Mathews, Edward Grochowski, Chakravarthy Kosaraju
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Publication number: 20020087825Abstract: An embodiment of the present invention includes a tag array, a valid vector, and a detector. The tag array stores N tag entries. Each of the N tag entries contains a one-hot tag having K bits. Each of the K bits of the one-hot tag corresponds to a translation look-aside buffer (TLB) entry in a TLB array having K TLB entries. The valid vector stores N valid entries corresponding to the N tag entries. The detector detects an error when a tag entry is read out upon a fetch read operation.Type: ApplicationFiled: December 28, 2000Publication date: July 4, 2002Inventors: Venkatesh Nagapudi, Chakravarthy Kosaraju
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Publication number: 20020073261Abstract: A method and apparatus in which an arbiter links to a processor having a flexible architecture, and the processor connects to a device through a point to point bus.Type: ApplicationFiled: December 13, 2000Publication date: June 13, 2002Inventor: Chakravarthy Kosaraju