Patents by Inventor Chakravarthy Srinivasan
Chakravarthy Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9209690Abstract: A spread-spectrum switching regulator for eliminating modulation ripple includes high gain amplifier that is responsive to reference voltage and feedback voltage of feedback loop to generate differential voltage, the feedback voltage being one of output voltage of the spread-spectrum switching regulator and a fraction of the output voltage; compensation circuit, coupled to the high gain amplifier, that maintains stability of the feedback loop to generate error level voltage in response to differential voltage; ramp generator that generates ramp waveform with slope adaptable to switching frequency to maintain duty cycle at constant value; pulse width modulator, coupled to compensation circuit and ramp generator, that compares error level voltage and ramp waveform to generate pulsed waveform; driver circuit, coupled to pulse width modulator, that drives the pulsed waveform to alternately switch a pair of transistors; and LC network, coupled to the pair of transistors, to average pulsed waveform to the output voType: GrantFiled: February 19, 2013Date of Patent: December 8, 2015Inventors: Chakravarthy Srinivasan, Pawan Gupta, Saumitra Singh
-
Publication number: 20140091774Abstract: A spread-spectrum switching regulator for eliminating modulation ripple includes high gain amplifier that is responsive to reference voltage and feedback voltage of feedback loop to generate differential voltage, the feedback voltage being one of output voltage of the spread-spectrum switching regulator and a fraction of the output voltage; compensation circuit, coupled to the high gain amplifier, that maintains stability of the feedback loop to generate error level voltage in response to differential voltage; ramp generator that generates ramp waveform with slope adaptable to switching frequency to maintain duty cycle at constant value; pulse width modulator, coupled to compensation circuit and ramp generator, that compares error level voltage and ramp waveform to generate pulsed waveform; driver circuit, coupled to pulse width modulator, that drives the pulsed waveform to alternately switch a pair of transistors; and LC network, coupled to the pair of transistors, to average pulsed waveform to the output voType: ApplicationFiled: February 19, 2013Publication date: April 3, 2014Applicant: CIREL SYSTEMS PRIVATE LIMITEDInventors: Chakravarthy Srinivasan, Pawan Gupta, Saumitra Singh
-
Patent number: 8671254Abstract: A wireless communications device has two or more multiple port memory units operable to perform encryption/decryption shuffling and processing. Other circuits and methods of manufacture and operation are also disclosed.Type: GrantFiled: September 1, 2011Date of Patent: March 11, 2014Assignee: Texas Instruments IncorporatedInventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
-
Patent number: 8237422Abstract: Efficient switch cascode architecture for switching devices, such as switching regulators. The cascode architecture includes a switching stage responsive to an external driver signal for switching transitions, and a bias generator operative to bias the cascode transistor of the switching stage to protect the switching stage from damage during the switching transitions.Type: GrantFiled: May 9, 2009Date of Patent: August 7, 2012Assignee: Cosmic Circuits Private LimitedInventors: Saumitra Singh, Rupak Ghayal, Chakravarthy Srinivasan, Prakash Easwaran
-
Publication number: 20120030447Abstract: A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line.Type: ApplicationFiled: September 1, 2011Publication date: February 2, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
-
Patent number: 8032762Abstract: A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line.Type: GrantFiled: September 2, 2009Date of Patent: October 4, 2011Assignee: Texas Instruments IncorporatedInventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
-
Publication number: 20100283439Abstract: Efficient switch cascode architecture for switching devices, such as switching regulators. The cascode architecture includes a switching stage responsive to an external driver signal for switching transitions, and a bias generator operative to bias the cascode transistor of the switching stage to protect the switching stage from damage during the switching transitions.Type: ApplicationFiled: May 9, 2009Publication date: November 11, 2010Applicant: COSMIC CIRCUITS PRIVATE LIMITEDInventors: Saumitra Singh, Rupak Ghayal, Chakravarthy Srinivasan, Prakash Easwaran
-
Patent number: 7821436Abstract: A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.Type: GrantFiled: June 9, 2007Date of Patent: October 26, 2010Assignee: Cosmic Circuits Private LimitedInventors: Venkatesh Teeka Srinvasa Setty, Chandrashekar Lakshminarayanan, Prasun Kali Bhattacharya, Prasenjit Bhowmik, Chakravarthy Srinivasan, Mukesh Khatri, Sanjeeb Kumar Ghosh, Sumanth Chakkirala, Sundararajan Krishnan, Prakash Easwaran
-
Publication number: 20090323951Abstract: A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line.Type: ApplicationFiled: September 2, 2009Publication date: December 31, 2009Applicant: Texas Instruments IncorporatedInventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
-
Patent number: 7602905Abstract: A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line.Type: GrantFiled: September 1, 2004Date of Patent: October 13, 2009Assignee: Texas Instruments IncorporatedInventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
-
Publication number: 20060056620Abstract: A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line.Type: ApplicationFiled: September 1, 2004Publication date: March 16, 2006Inventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
-
Patent number: 6747589Abstract: An SAR ADC is operated by sampling an input voltage and redistributing a corresponding charge among the coupling capacitor and a plurality of binarily weighted capacitors of a CDAC array to produce a first voltage on a charge summing conductor. A successive approximation bit testing/conversion operation is performed at a first speed on a first group of bits, beginning with the MSB, to determine the bits of the first group with at least a first level of accuracy. A first error correction operation includes performing a bit testing/conversion operation on a last bit of the first group at a second speed which is lower than the first speed to determine the bits of the first group at least a second level of accuracy which is more accurate than the first level of accuracy. Both the voltage on the charge summing conductor and the bits of the group are incremented or decremented as necessary to elevate the level of accuracy of bits of the first group to at least the second level of accuracy.Type: GrantFiled: May 21, 2002Date of Patent: June 8, 2004Assignee: Texas Instruments IncorporatedInventors: Chakravarthy Srinivasan, Kiran M. Godbole
-
Publication number: 20030123646Abstract: An SAR ADC is operated by sampling an input voltage and redistributing a corresponding charge among the coupling capacitor and a plurality of binarily weighted capacitors of a CDAC array to produce a first voltage on a charge summing conductor. A successive approximation bit testing/conversion operation is performed at a first speed on a first group of bits, beginning with the MSB, to determine the bits of the first group with at least a first level of accuracy. A first error correction operation includes performing a bit testing/conversion operation on a last bit of the first group at a second speed which is lower than the first speed to determine the bits of the first group at least a second level of accuracy which is more accurate than the first level of accuracy. Both the voltage on the charge summing conductor and the bits of the group are incremented or decremented as necessary to elevate the level of accuracy of bits of the first group to at least the second level of accuracy.Type: ApplicationFiled: May 21, 2002Publication date: July 3, 2003Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Chakravarthy Srinivasan, Kiran M. Godbole