Patents by Inventor Chakri PADALA

Chakri PADALA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250094350
    Abstract: A method of cache pooling is presented where the method includes determining whether a cache of a primary processor assigned to execute an application has insufficient storage space to allot for the application, select at least one alternative processor from a list of alternative processors based on a cache availability or metric for each processor in the list of alternative processors, configuring the primary processor and the selected at least one alternative processor for mutual cache visibility, and configure routing of traffic to the application to be divided between the primary processor cache and the selected at least one alternative processor cache.
    Type: Application
    Filed: October 14, 2021
    Publication date: March 20, 2025
    Applicant: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Amir ROOZBEH, Chakri PADALA, Alireza FARSHIN
  • Patent number: 12222854
    Abstract: There is provided mechanisms for initiating writing data of a pending memory write on a host computer. A method comprises monitoring pending memory writes for a non-volatile memory write indicator (NVMWI). The NVMWI is either set or not set. The method comprises initiating writing of the data of the pending memory write. Writing of the data is initiated to both a non-volatile memory (NVM) and a volatile memory (VM) when the NVMWI for the pending memory write is set. Writing of the data otherwise is initiated only to the VM.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: February 11, 2025
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Ahsan Javed Awan, Amir Roozbeh, Chakri Padala
  • Patent number: 12190153
    Abstract: In a M2M device management system, a Task Orchestration Module, TOM (32) external to the M2M device (20) manages the execution of tasks wholly or partly on the M2M device (20). This alleviates the M2M device (20) of the need to store code, execute tasks, monitor task execution, and the like. The tasks are specified using Finite State Machine, FSM, syntax. A task URL, tURL (34) resource on the M2M device (20) provides a tURL (34) to a resource hosting (36) a service (38) mapping task-IDs to FSM specifications. Communications between the TOM (32) and M2M device (20) is compactly and efficiently achieved using a device management protocol server/client system (16, 18), such as LightWeightM2M (LWM2M). A predetermined mapping (40) at the M2M device (20) maps action labels to library functions (22) of the M2M device (20), obviating the need for code in the M2M device (20) to interpret and execute actions.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: January 7, 2025
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Swarup Kumar Mohalik, Senthamiz Selvi Arumugam, Chakri Padala
  • Patent number: 12032481
    Abstract: A method performed by a coordinating entity in a disaggregated data center architecture wherein computing resources are separated in discrete resource pools and associated together to represent a functional server. The coordinating entity obtains a setup of processor cores that are coupled logically as the functional server, and determines an index indicating an identity of a cache coherency domain based on the obtained setup of processor cores. The coordinating entity further configures one or more communicating entities associated with the obtained setup of processor cores, to use the determined index when handling updated cache related data.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: July 9, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Chakri Padala, Amir Roozbeh, Ahsan Javed Awan
  • Patent number: 12013783
    Abstract: There is provided mechanisms for snapshotting data of a host application. A method is performed by a field-programmable gate array (FPGA). The method comprises snooping a cache coherent interconnect of a host computer on which the host application is running. The cache coherent interconnect is snooped for dirty cache lines, each dirty cache line having an address. The method comprises writing, only when the address of any of the dirty cache lines has a match in a snapshot address table, data of that dirty cache line to a non-volatile memory.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: June 18, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Ahsan Javed Awan, Amir Roozbeh, Chakri Padala
  • Patent number: 11960926
    Abstract: An artificial intelligence, AI, planning controller control the timing of when a plan (16) to accomplish a task (14) is synthesized. The AI planning controller in this regard determines a quiescent phase (20) during which values of at least some predicates describing a state of the system (12) will remain stable. The AI planning controller then controls artificial intelligence planning to synthesize the plan (16) during at least some of the quiescent phase (20).
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: April 16, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Swarup Kumar Mohalik, Senthamiz Selvi Arumugam, Chakri Padala
  • Publication number: 20230409472
    Abstract: There is provided mechanisms for initiating writing data of a pending memory write on a host computer. A method comprises monitoring pending memory writes for a non-volatile memory write indicator (NVMWI). The NVMWI is either set or not set. The method comprises initiating writing of the data of the pending memory write. Writing of the data is initiated to both a non-volatile memory (NVM) and a volatile memory (VM) when the NVMWI for the pending memory write is set. Writing of the data otherwise is initiated only to the VM.
    Type: Application
    Filed: December 22, 2020
    Publication date: December 21, 2023
    Inventors: Ahsan Javed Awan, Amir Roozbeh, Chakri Padala
  • Publication number: 20230385197
    Abstract: A method performed by a coordinating entity in a disaggregated data center architecture wherein computing resources are separated in discrete resource pools and associated together to represent a functional server. The coordinating entity obtains a setup of processor cores that are coupled logically as the functional server, and determines an index indicating an identity of a cache coherency domain based on the obtained setup of processor cores. The coordinating entity further configures one or more communicating entities associated with the obtained setup of processor cores, to use the determined index when handling updated cache related data.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Applicant: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Chakri PADALA, Amir ROOZBEH, Ahsan Javed AWAN
  • Patent number: 11797342
    Abstract: A method and a supporting node (150) for supporting a process scheduling node (110) when scheduling a process to a first execution node (130) of a cluster (120) of execution nodes (130, 140, 150) are disclosed. The supporting node (150) receives (A140), from the first execution node (130) being selected by the process scheduling node (110) for execution of the process, a request for allocation of one or more HA devices (131, 141, 151). The supporting node (150) allocates at least one HA device (141), being associated with a second execution node (140) of the cluster (120), to the first execution node (130). The supporting node (150) reduces a value representing number of HA devices (131, 141, 151) available for allocation to the first execution node (130) while taking said at least one HA device (141) into account. The supporting node (150) sends the value to the first execution node (130).
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: October 24, 2023
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Chakri Padala, Nhi Vo, Mozhgan Mahloo, Joao Monteiro Soares
  • Patent number: 11757742
    Abstract: A system and method to distribute traffic flows among a plurality of applications in a data center system. An apparatus is operable with a plurality of applications connected through a programmable switch and is configured to select traffic flows to ones of the plurality of applications. The apparatus is also configured to monitor and collect statistics for the traffic flows to determine rule level statistics, and move at least one traffic flow of the traffic flows from a network interface to a different network interface based on the rule level statistics.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 12, 2023
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Chakri Padala, Prasanna Huddar, Amir Roozbeh, Ahsan Javed Awan
  • Patent number: 11755482
    Abstract: A method performed by a coordinating entity in a disaggregated data center architecture wherein computing resources are separated in discrete resource pools and associated together to represent a functional server. The coordinating entity obtains a setup of processor cores that are coupled logically as the functional server, and determines an index indicating an identity of a cache coherency domain based on the obtained setup of processor cores. The coordinating entity further configures one or more communicating entities associated with the obtained setup of processor cores, to use the determined index when handling updated cache related data.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: September 12, 2023
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Chakri Padala, Amir Roozbeh, Ahsan Javed Awan
  • Patent number: 11733906
    Abstract: A data storage system in which different copies of a data object (e.g., a file) can be compressed using different compression processes (e.g. different compression algorithms/processes and/or compression parameters), with some favoring faster decompression, while others favoring storage space savings. When a data object needs to be accessed, the copy of the data object that can be decompressed using minimal resource (computing and/or time) can be located and retrieved.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: August 22, 2023
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Chakri Padala, Ganapathy Raman Madanagopal, Ashis Kumar Roy, Dinesh Yadav
  • Patent number: 11722383
    Abstract: A method in a network node is provided for mitigating disruption during maintenance of an edge gateway node of a communication network. The edge gateway node connects devices to services(s) of the communication network. First device(s) are capable of connecting to a cloud environment in the absence of the edge gateway node, and second device(s) are incapable of connecting to the cloud environment in the absence of the edge gateway node. The method comprises: establishing respective virtual devices for the second device(s), the virtual devices comprising predictive models trained to replicate data output by the respective second device(s); and, during a time interval in which the maintenance of the edge gateway node is performed: configuring the virtual device(s) to connect to a virtual edge gateway node established in the cloud environment; and configuring at least one of the first device(s) to connect to the virtual edge gateway node.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 8, 2023
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Swarup Kumar Mohalik, Sambit Nayak, Chakri Padala
  • Publication number: 20230185716
    Abstract: There is provided mechanisms for snapshotting data of a host application. A method is performed by a field-programmable gate array (FPGA). The method comprises snooping a cache coherent interconnect of a host computer on which the host application is running. The cache coherent interconnect is snooped for dirty cache lines, each dirty cache line having an address. The method comprises writing, only when the address of any of the dirty cache lines has a match in a snapshot address table, data of that dirty cache line to a non-volatile memory.
    Type: Application
    Filed: March 4, 2020
    Publication date: June 15, 2023
    Applicant: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Ahsan Javed AWAN, Amir ROOZBEH, Chakri PADALA
  • Publication number: 20220342822
    Abstract: A method performed by a coordinating entity in a disaggregated data center architecture wherein computing resources are separated in discrete resource pools and associated together to represent a functional server. The coordinating entity obtains a setup of processor cores that are coupled logically as the functional server, and determines an index indicating an identity of a cache coherency domain based on the obtained setup of processor cores. The coordinating entity further configures one or more communicating entities associated with the obtained setup of processor cores, to use the determined index when handling updated cache related data.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 27, 2022
    Applicant: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Chakri PADALA, Amir ROOZBEH, Ahsan Javed AWAN
  • Publication number: 20220278911
    Abstract: A system and method to distribute traffic flows among a plurality of applications in a data center system. An apparatus is operable with a plurality of applications connected through a programmable switch and is configured to select traffic flows to ones of the plurality of applications. The apparatus is also configured to monitor and collect statistics for the traffic flows to determine rule level statistics, and move at least one traffic flow of the traffic flows from a network interface to a different network interface based on the rule level statistics.
    Type: Application
    Filed: August 23, 2019
    Publication date: September 1, 2022
    Applicant: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Chakri PADALA, Prasanna HUDDAR, Amir ROOZBEH, Ahsan Javed AWAN
  • Patent number: 11416299
    Abstract: A method and a resource scheduler for enabling a computing unit to use memory resources in a remote memory pool. The resource scheduler allocates a memory unit in the remote memory pool to the computing unit for usage of memory resources in the allocated memory unit, and assigns an optical wavelength for communication between the computing unit and the allocated memory unit over an optical network. The resource scheduler further configures at least the computing unit with a first mapping between the assigned optical wavelength and the allocated memory unit. Thereby, the optical network can be utilized efficiently to achieve rapid and reliable communication of messages from the computing unit to the allocated memory unit.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 16, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Joao Monteiro Soares, Chakri Padala, Amir Roozbeh, Mozhgan Mahloo
  • Patent number: 11409565
    Abstract: A computing unit, a memory pool and methods therein, for enabling the computing unit to use memory resources in the memory pool, e.g. as configured by a resource scheduler. When a memory unit in the memory pool is allocated to the computing unit and an optical wavelength is assigned for communication between the computing unit and the allocated memory unit over an optical network, the computing unit is configured with a first mapping between the assigned optical wavelength and the allocated memory unit. Thereby, the optical network can be utilized efficiently to achieve rapid and reliable communication of messages from the computing unit to the allocated memory unit.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 9, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Joao Monteiro Soares, Amir Roozbeh, Mozhgan Mahloo, Chakri Padala
  • Publication number: 20220166687
    Abstract: A method in a network node is provided for mitigating disruption during maintenance of an edge gateway node of a communication network. The edge gateway node connects devices to services(s) of the communication network. First device(s) are capable of connecting to a cloud environment in the absence of the edge gateway node, and second device(s) are incapable of connecting to the cloud environment in the absence of the edge gateway node. The method comprises: establishing respective virtual devices for the second device(s), the virtual devices comprising predictive models trained to replicate data output by the respective second device(s); and, during a time interval in which the maintenance of the edge gateway node is performed: configuring the virtual device(s) to connect to a virtual edge gateway node established in the cloud environment; and configuring at least one of the first device(s) to connect to the virtual edge gateway node.
    Type: Application
    Filed: February 22, 2019
    Publication date: May 26, 2022
    Inventors: Swarup Kumar MOHALIK, Sambit NAYAK, Chakri PADALA
  • Patent number: 11340949
    Abstract: A method and a hardware acceleration managing node for managing a request for hardware acceleration (HA). The hardware acceleration managing node receives, from a HA interfacing node, the request for hardware acceleration of processing of source data. The hardware acceleration managing node sends an indication of a source memory location(s) for storing of the source data. The hardware acceleration managing node selects one or more hardware acceleration devices. The hardware acceleration managing node receives a chunk of code to be accelerated. The hardware acceleration managing node sends, to the one hardware acceleration device, a set of acceleration instructions related to the chunk of code and the indication of the source memory location. The hardware acceleration managing node receives an indication of a result memory location indicating result data. The hardware acceleration managing node sends an indication of completed hardware acceleration to the HA interfacing node.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: May 24, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Chakri Padala, Mozhgan Mahloo, Joao Monteiro Soares, Nhi Vo