Patents by Inventor Chaminda N. Vidanagamachchi
Chaminda N. Vidanagamachchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240107086Abstract: A non-transitory computer readable medium may include instructions that, when executed by at least one computer processor, cause the at least one computer processor to obtain an initial image frame at a first resolution. The initial frame may include a first number of pixels. The at least one computer processor may be caused to generate a downscaled image frame from the initial image frame at a second resolution. The at least one computer processor may be caused to obtain one or more subframes of the initial image frame. Each of the subframes may include a portion of the number of pixels. The at least one computer processor may be caused to transmit, to a playback device, the downscaled image frame and at least one of the subframes. The downscaled image frame and the subframe may be combinable to form a target frame comprising subframes of differing resolutions.Type: ApplicationFiled: August 29, 2023Publication date: March 28, 2024Inventors: Chaminda N. Vidanagamachchi, Matthew J. Yaeger
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Publication number: 20240107154Abstract: An apparatus includes a primary camera sensor configured to capture images having a first resolution, a primary processing circuit configured to process images captured by the primary camera sensor, a secondary camera sensor configured to capture images having a second resolution, and a secondary processing circuit configured to process images captured by the secondary camera sensor. In response to a determination that a particular object of interest is included in a particular image, the secondary processing circuit may be further configured to cause the primary processing circuit and the primary camera sensor to exit a reduced power mode. The primary camera sensor may be further configured, in response to the exiting, to capture a different image. The primary processing circuit may also be configured to process the different image to validate the particular object of interest.Type: ApplicationFiled: October 4, 2023Publication date: March 28, 2024Inventors: Paolo Di Febbo, Chaminda N. Vidanagamachchi, Yohan Rajan, Anselm Grundhoefer
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Publication number: 20240005972Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.Type: ApplicationFiled: July 3, 2023Publication date: January 4, 2024Inventors: Paolo Di Febbo, Mohamed H. Abu-Rahma, Jelam K. Parekh, Yildiz Sinangil, Mohammad Ghasemzadeh, Anthony Ghannoum, Chaminda N. Vidanagamachchi
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Patent number: 11792507Abstract: An apparatus includes a primary camera sensor configured to capture images having a first resolution, a primary processing circuit configured to process images captured by the primary camera sensor, a secondary camera sensor configured to capture images having a second resolution, and a secondary processing circuit configured to process images captured by the secondary camera sensor. In response to a determination that a particular object of interest is included in a particular image, the secondary processing circuit may be further configured to cause the primary processing circuit and the primary camera sensor to exit a reduced power mode. The primary camera sensor may be further configured, in response to the exiting, to capture a different image. The primary processing circuit may also be configured to process the different image to validate the particular object of interest.Type: GrantFiled: January 15, 2021Date of Patent: October 17, 2023Assignee: Apple Inc.Inventors: Paolo Di Febbo, Chaminda N. Vidanagamachchi, Yohan Rajan, Anselm Grundhoefer
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Patent number: 11755854Abstract: Various implementations disclosed herein include multi-scale visual markers that convey information in multiple sets of markings using different respective appearance attributes. In some implementations, the appearance attribute of the markings of a first set of markings corresponds to a first encoding parameter and the appearance attribute of markings of a second set of markings corresponds to a second encoding parameter different from the first encoding parameter. In some implementations, the first set of markings encode first data and the second set of markings are different than the first set of markings and encode second data. In some implementations, the different appearance attributes are different scales (e.g., different sizes, different numbers of markings per unit of space, different contrast, different color characteristics, different wavelengths, different image sensor types, etc.).Type: GrantFiled: June 17, 2021Date of Patent: September 12, 2023Assignee: Apple Inc.Inventors: Paolo Di Febbo, Chaminda N. Vidanagamachchi, Waleed Abdulla, Yohan Rajan
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Patent number: 11694733Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.Type: GrantFiled: August 19, 2021Date of Patent: July 4, 2023Assignee: Apple Inc.Inventors: Paolo Di Febbo, Mohamed H. Abu-Rahma, Jelam K. Parekh, Yildiz Sinangil, Mohammad Ghasemzadeh, Anthony Ghannoum, Chaminda N. Vidanagamachchi
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Publication number: 20230206050Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.Type: ApplicationFiled: February 24, 2023Publication date: June 29, 2023Inventors: Paolo Di Febbo, Waleed Abdulla, Chaminda N Vidanagamachchi, Yohan Rajan
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Patent number: 11593628Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.Type: GrantFiled: March 5, 2020Date of Patent: February 28, 2023Assignee: Apple Inc.Inventors: Paolo Di Febbo, Waleed Abdulla, Chaminda N. Vidanagamachchi, Yohan Rajan
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Publication number: 20230059200Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.Type: ApplicationFiled: August 19, 2021Publication date: February 23, 2023Inventors: Paolo Di Febbo, Mohamed H. Abu-Rahma, Jelam K. Parekh, Yildiz Sinangil, Mohammad Ghasemzadeh, Anthony Ghannoum, Chaminda N. Vidanagamachchi
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Publication number: 20220019752Abstract: Various implementations disclosed herein include multi-scale visual markers that convey information in multiple sets of markings using different respective appearance attributes. In some implementations, the appearance attribute of the markings of a first set of markings corresponds to a first encoding parameter and the appearance attribute of markings of a second set of markings corresponds to a second encoding parameter different from the first encoding parameter. In some implementations, the first set of markings encode first data and the second set of markings are different than the first set of markings and encode second data. In some implementations, the different appearance attributes are different scales (e.g., different sizes, different numbers of markings per unit of space, different contrast, different color characteristics, different wavelengths, different image sensor types, etc.).Type: ApplicationFiled: June 17, 2021Publication date: January 20, 2022Inventors: Paolo Di Febbo, Chaminda N. Vidanagamachchi, Waleed Abdulla, Yohan Rajan
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Publication number: 20210279557Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.Type: ApplicationFiled: March 5, 2020Publication date: September 9, 2021Inventors: Paolo Di Febbo, Waleed Abdulla, Chaminda N. Vidanagamachchi, Yohan Rajan