Patents by Inventor Chan BAE

Chan BAE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090284125
    Abstract: A plasma display panel includes first and second substrates facing each other and spaced apart from each other, barrier ribs arranged between the first and second substrates to define discharge cells, phosphor layers in the discharge cells, address electrodes extending on the first substrate along a first direction to correspond to the discharge cells, first and second electrodes extending on the second substrate along a second direction to correspond to the discharge cells, the second direction crossing the first direction, a dielectric layer on the first and second electrodes, and a doped protective layer on the dielectric layer, the protective layer including at least one groove.
    Type: Application
    Filed: May 14, 2009
    Publication date: November 19, 2009
    Inventors: Seong-chan BAE, Chun-Gyoo LEE
  • Publication number: 20090260720
    Abstract: Provided is a Nd-based two-phase separation amorphous alloy by adding an element having a big difference in heat of mixing in a Nd-based alloy with a superior amorphous formability through an inherent characteristic of compositional elements and consideration of thermodynamics, at the time of forming amorphous phase, to thereby enable two-phase separation amorphous alloy during solidification.
    Type: Application
    Filed: February 10, 2009
    Publication date: October 22, 2009
    Inventors: Eun Soo Park, Hye Jung Chang, Do Hyang Kim, Eun Young Jeong, Jin Kyu Lee, Hwi Jun Kim, Jung Chan Bae
  • Publication number: 20090115019
    Abstract: The semiconductor device having an air gap includes an insulation layer formed on a semiconductor substrate and having a metal line forming region. A metal line is formed to fill the metal line forming region of the insulation layer. An air gap is formed between the insulation layer and the metal line.
    Type: Application
    Filed: May 21, 2008
    Publication date: May 7, 2009
    Inventors: Hyo Seok LEE, Jong Min LEE, Chan Bae KIM, Chai O CHUNG, Hyeon Ju AN, Sung Kyu MIN
  • Publication number: 20090001044
    Abstract: A process for manufacturing a semiconductor device using a spacer as an etch mask for forming a fine pattern is described. The process includes forming a hard mask layer over a target layer that is desired to be etched. A sacrificial layer pattern is subsequently formed over the hard mask layer. Spacers are formed on the sidewalls of the sacrificial layer pattern. The protective layer is formed on the hard mask layer portions between the sacrificial patterns formed with the spacer. The sacrificial layer pattern and the protective layer are then later removed, respectively. The hard mask layer is etched using the spacer as an etching mask. After etching, the spacer is removed. Finally, the target layer is etched using the etched hard mask as an etching mask.
    Type: Application
    Filed: November 13, 2007
    Publication date: January 1, 2009
    Inventors: Chai O. CHUNG, Jong Min LEE, Chan Bae KIM, Hyeon Ju AN, Hyo Seok LEE, Sung Kyu MIN
  • Publication number: 20080318437
    Abstract: A semiconductor device is manufactured by forming a low dielectric constant layer on a semiconductor substrate which is formed with metal lines; implementing primary ultraviolet treatment of the low dielectric constant layer; forming a capping layer on the low dielectric constant layer having undergone the primary ultraviolet treatment; and implementing secondary ultraviolet treatment of the low dielectric constant layer including the capping layer.
    Type: Application
    Filed: August 6, 2007
    Publication date: December 25, 2008
    Inventors: Chan Bae Kim, Jong Min Lee, Chae O Chung, Hyeon Ju An, Hyo Seok Lee, Sung Kyu Min
  • Patent number: 7439177
    Abstract: In manufacturing a semiconductor device, a metal film is formed on a semiconductor substrate, and a high-temperature amorphous carbon film pattern for defining a wiring forming area is formed on the metal film. The metal film is etched by using the high-temperature amorphous carbon film pattern as an etching barrier to form a metal wiring. A low-temperature amorphous carbon film as an IMD is formed on the resultant structure so as to cover the metal wiring including the high-temperature amorphous carbon film pattern. The low-temperature amorphous carbon film and the high-temperature amorphous carbon film pattern are etched to form a contact hole, which has greater width in an upper portion than in a lower portion thereof. Finally, a plug metal film is formed on the low-temperature amorphous carbon film to fill the contact hole.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: October 21, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chan Bae Kim, Chai O Chung
  • Publication number: 20080246359
    Abstract: Disclosed are a motor and a drum washing machine having the same. The motor includes external stators and internal stators, which are respectively disposed in a ring shape and are separated from each other in a radial direction, and rotors, which are disposed in a ring shape and are rotatably installed between the external stators and the internal stators such that the rotors are rotated due to interaction with the external stators and the internal stators, thus being capable of generating a high rotary force while maintaining a uniform length in an axial direction.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 9, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jang Jun Lee, Chan Bae Park
  • Publication number: 20080214018
    Abstract: A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer.
    Type: Application
    Filed: December 27, 2007
    Publication date: September 4, 2008
    Inventors: Sung Kyu MIN, Ja Chun KU, Chan Bae KIM, Sang Tae AHN, Chai O. CHUNG, Hyeon Ju AN, Hyo Seok LEE, Eun Jeong KIM
  • Patent number: 7313910
    Abstract: Disclosed is a jet vane thrust vector control (JV-TVC) system. A general system has many problems in design techniques considering actual operation environments, and does not have reliability in component assembly design. The JV-TVC system improves thrust vector control and high angle of attack maneuvering performance of a missile by allowing rotational angles of jet vanes to maximum ±30°, precisely controls the thrust vector of the missile by preventing damages of components for the designated flight time of the missile, and improves precision and reliability in the assembly process by modularization.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: January 1, 2008
    Assignee: Agency for Defense Development
    Inventors: Won-Hoon Kim, Joo-Chan Bae, Seong-Taek Lim, Sung-Han Park
  • Publication number: 20070258846
    Abstract: Provided is a Nd-based two-phase separation amorphous alloy by adding an element having a big difference in heat of mixing in a Nd-based alloy with a superior amorphous formability through an inherent characteristic of compositional elements and consideration of thermodynamics, at the time of forming amorphous phase, to thereby enable two-phase separation amorphous alloy during solidification.
    Type: Application
    Filed: February 27, 2007
    Publication date: November 8, 2007
    Inventors: Eun Soo Park, Hye Jung Chang, Do Hyang Kim, Eun Young Jeong, Jin Kyu Lee, Hwi Jun Kim, Jung Chan Bae
  • Publication number: 20050178878
    Abstract: Disclosed is a jet vane thrust vector control (JV-TVC) system. A general system has many problems in design techniques considering actual operation environments, and does not have reliability in component assembly design. The JV-TVC system improves thrust vector control and high angle of attack maneuvering performance of a missile by allowing rotational angles of jet vanes to maximum ±30°, precisely controls the thrust vector of the missile by preventing damages of components for the designated flight time of the missile, and improves precision and reliability in the assembly process by modularization.
    Type: Application
    Filed: December 30, 2004
    Publication date: August 18, 2005
    Applicant: AGENCY FOR DEFENSE DEVELOPMENT
    Inventors: Won-Hoon Kim, Joo-Chan Bae, Seong-Taek Lim, Sung-Han Park
  • Patent number: 6562679
    Abstract: A method for forming the storage node of a capacitor which simplifies its process, and improves the electrical characteristics of semiconductor products by forming the storage node of a capacitor with no stepped portion between cell regions and peripheral circuit regions necessary for memory storage of semiconductor products of the next generation to which a fine line width is applied, and, at the same time, forming a guard ring for dividing the cell regions and the peripheral circuit regions.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: May 13, 2003
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Kee-jeung Lee, Seoung-wook Lee, Seung-hyuk Lee, Chan-bae Kim, Wan-gie Lee
  • Patent number: 6531446
    Abstract: The present invention relates to peptides that are more potent than or equally potent as the conventional antimicrobial peptides and has strong antimicrobial activities at high salt concentration.
    Type: Grant
    Filed: November 2, 2000
    Date of Patent: March 11, 2003
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Sun-Chang Kim, Chan-Bae Park, Jae-Hyun Lee, Seung-Suh Hong, Hyun-Soo Lee
  • Publication number: 20020106856
    Abstract: A method for forming the storage node of a capacitor which simplifies its process, and improves the electrical characteristics of semiconductor products by forming the storage node of a capacitor with no stepped portion between cell regions and peripheral circuit regions necessary for memory storage of semiconductor products of the next generation to which a fine line width is applied, and, at the same time, forming a guard ring for dividing the cell regions and the peripheral circuit regions.
    Type: Application
    Filed: August 22, 2001
    Publication date: August 8, 2002
    Inventors: Kee-Jeung Lee, Seoung-Wook Lee, Seung-Hyuk Lee, Chan-Bae Kim, Wan-Gie Lee
  • Patent number: D557244
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: December 11, 2007
    Assignee: LG Electronics Inc.
    Inventors: Seung Il Lee, Bo Ra Choi, Youn Chan Bae, Seon Woo Yoo
  • Patent number: D557673
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: December 18, 2007
    Assignee: LG Electronics Inc.
    Inventors: Seung Il Lee, Bo Ra Choi, Youn Chan Bae, Seon Woo Yoo
  • Patent number: D557674
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: December 18, 2007
    Assignee: LG Electronics Inc.
    Inventors: Seung Il Lee, Bo Ra Choi, Youn Chan Bae, Seon Woo Yoo
  • Patent number: D563933
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: March 11, 2008
    Assignee: LG Electronics Inc.
    Inventors: Seung Il Lee, Bo Ra Choi, Youn Chan Bae, Seon Woo Yoo
  • Patent number: D580397
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: November 11, 2008
    Assignee: LG Electronics Inc.
    Inventors: Ki Yeoul Seo, Ho Phil Lee, Joung Young Joung, Youn Chan Bae, Seon Woo Yoo
  • Patent number: D593979
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: June 9, 2009
    Assignee: LG Electronics Inc.
    Inventors: Seung Il Lee, Bo Ra Choi, Youn Chan Bae, Seon Woo Yoo