Patents by Inventor Chan-chan LIN

Chan-chan LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230197895
    Abstract: A light emitting diode includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, a light emitting layer, and a stress relief layer. The second conductivity-type semiconductor layer has a conductivity type opposite to that of the first conductivity-type semiconductor layer. The light emitting layer is disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer. The stress relief layer is disposed between the first conductivity-type semiconductor layer and the light emitting layer, and includes well layers and barrier layers stacked alternately. The stress relief layer further includes at least one blocking zone in at least one of the well layers. The at least one blocking zone has an energy gap greater than an energy gap of the at least one of the well layers. A method for manufacturing the light emitting diode is also disclosed.
    Type: Application
    Filed: February 24, 2023
    Publication date: June 22, 2023
    Inventors: Zhibo XU, Zhihua ZHANG, Mingbin MA, Cheng-Hung LEE, Chan-Chan LIN, Chia-Hao CHANG
  • Publication number: 20170117436
    Abstract: A fabrication method of a nitride semiconductor LED includes, an AlxInyGa1-x-yN material layer is deposited by CVD between an AlN thin film layer by PVD and a gallium nitride series layer by CVD, to reduce the stress effect between the AlN thin film layer and the nitride layer, improve the overall quality of the LED and efficiency. An AlN thin film layer is deposited on a patterned substrate having a larger depth by PVD, and a thin nitrogen epitaxial layer is deposited on the AlN thin film layer by CVD, which reduces the stress by reducing the thickness of the epitaxial layer and improves warpage of the wafer and electric uniformity of the single wafer; the light extraction efficiency is improved by using the large depth patterned substrate; further, the doping of high-concentration impurity in the active layer effectively reduces voltage characteristics without affecting leakage, thereby improving the overall yield.
    Type: Application
    Filed: January 8, 2017
    Publication date: April 27, 2017
    Applicant: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hsiang-lin HSIEH, Zhibo XU, Cheng-hung LEE, Chan-chan LIN, Chang-cheng CHUO, Chia-hung CHANG