Patents by Inventor Chan Chee Ling

Chan Chee Ling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7186588
    Abstract: A method of fabricating a micro-array IC package is recited. A wafer has a B-stageable adhesive applied, and the wafer is diced. The individual dice are applied to a lead-frame via their adhesive, and wirebonded to associated leads. The lead-frame is then encapsulated, and solder connectors are applied. The lead-frame is then singulated to produce a plurality of lead-frame based micro-array packages. The process thus allows lead-frame based manufacturing methods to be employed in the production of BGA-type packages, allowing such packages to be produced faster and more efficiently.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: March 6, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Jaime A. Bayan, Santhiran S/O Nadarajah, Chan Chee Ling, Ashok S. Prabhu, Hasfiza Ramley, Chan Peng Yeen
  • Patent number: 7064419
    Abstract: A die attach region for use in an IC package is described. The die attach region employs a number of posts interconnected with a number of support risers to provide a structure that upholds a semiconductor die while facilitating flow of an encapsulant material underneath the die during encapsulation. The posts and risers can be arranged in a number of configurations that each facilitate flow of encapsulant material. This die attach region can be incorporated into a lead-frame structure or a substrate panel for ease and efficiency of manufacture.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: June 20, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Jaime A. Bayan, Ashok S. Prabhu, Chan Chee Ling, Lye Meng Kong, Santhiran S O Nadarajah