Abstract: A method for transmitting data from a timing controller to a source driver includes: applying a plurality of data rates to a discrete data rate setting; and transmitting image data of a plurality of frames by using the plurality of data rates, respectively, wherein for each of the frames, its corresponding image data is transmitting by using only one of the data rates.

Abstract: A signal transmitting and receiving system of a display includes a timing controller and at least one source driver. The timing controller is arranged for transmitting a training signal and a data signal. The source driver is coupled to the timing controller via at least one data channel and a lock channel, and is arranged for receiving the training signal and the data signal via the data channel. The timing controller transmits the training signal or the data signal to the source driver by referring to a voltage level of the lock channel, and the voltage level of the lock channel is allowed to be controlled by both the timing controller and the source driver.

Abstract: A signal transmitting and receiving system of a display includes a timing controller and at least one source driver. The timing controller is arranged for transmitting a training signal and a data signal. The source driver is coupled to the timing controller via at least one data channel and a lock channel, and is arranged for receiving the training signal and the data signal via the data channel. The timing controller transmits the training signal or the data signal to the source driver by referring to a voltage level of the lock channel, and the voltage level of the lock channel is allowed to be controlled by both the timing controller and the source driver.

Abstract: A method for transmitting data from a timing controller to a source driver includes: applying a plurality of data rates to a discrete data rate setting; and transmitting image data of a plurality of frames by using the plurality of data rates, respectively, wherein for each of the frames, its corresponding image data is transmitting by using only one of the data rates.

Abstract: A display device includes a printed circuit board, a timing controller, a display panel, a plurality of source drivers, and a plurality of traces. The timing controller is disposed on the printed circuit board for generating a plenty of differential pairs. The source drivers which are disposed on the display panel for receiving the differential pairs are respectively assigned with an identification number, in which each of the source drivers determines a polarity of the differential pair received according to a corresponding identification number assigned to the source driver. Flexible printed circuit boards are connected to the printed circuit board and the display panel, and each of the flexible printed circuit boards is corresponding to some of the source drivers. The traces carrying the differential pairs are connected to the timing controller and to the source drivers through the flexible printed circuit boards.

Abstract: A multi-phase clock generator including a first delay locked loop, a reference signal generator and a second delay locked loop is provided. The first delay locked loop generates 2N phase clock signals according to an input clock signal, so as to equally divide a clock period of the input clock signal into 2N predetermined phases, where N is a positive integer. The reference signal generator selects two phase clock signals according to a digital signal, and adjusts an output ratio of the two phase clock signals in 2M clock periods to serve as a reference clock signal. The second delay locked loop delays a first phase clock signal according to a phase difference between the reference clock signal and an output clock signal. In this way, each predetermined phase is further equally divided into 2M sub-phases, so that the multi-phase clock generator has 2(N+M) phase selections.

Abstract: A multi-phase clock generator including a first delay locked loop, a reference signal generator and a second delay locked loop is provided. The first delay locked loop generates 2N phase clock signals according to an input clock signal, so as to equally divide a clock period of the input clock signal into 2N predetermined phases, where N is a positive integer. The reference signal generator selects two phase clock signals according to a digital signal, and adjusts an output ratio of the two phase clock signals in 2M clock periods to serve as a reference clock signal. The second delay locked loop delays a first phase clock signal according to a phase difference between the reference clock signal and an output clock signal. In this way, each predetermined phase is further equally divided into 2M sub-phases, so that the multi-phase clock generator has 2(N+M) phase selections.

Abstract: A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal.

Abstract: A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal.