Abstract: An embodiment of the present disclosure may provide a method of detecting a fault location using an acoustic emission signal, including a measuring step of measuring, by a signal measuring unit including at least three sensors disposed in a diagnosed subject and isolated from one another, an acoustic emission signal generated from a faulty part of the diagnosed subject, a signal pre-processing step of filtering and amplifying, by the signal pre-processing unit, the acoustic emission signal, an extraction step of extracting, by a data operation unit, a measuring time, that is, the time when the acoustic emission signal reaches each of the at least three sensors of the signal measuring unit, and a first analysis step of analyzing, by a data analysis unit, a location and occurrence time of the faulty part by using the measuring time and location information of the signal measuring unit.

Abstract: A data processing device includes a controller. The controller includes a compression circuit configured to compare a plurality of data groups, each of which has a first burst length and is transmitted in units of an input/output width, with a predetermined pattern, and perform data compression on the data groups based on a result of comparison. The controller further includes a compression data restructuring circuit configured to generate a transmission data group by restructuring the compressed data group to have a second burst length.

Abstract: Disclosed is a backlight unit and LCD device having a fixing device attached to a bottom cover and a guide panel to prevent the guide panel from shifting and detaching from the bottom cover. The backlight unit comprises a bottom cover having a bottom portion including a first hole, and a side portion having a second hole; a light guide plate on the bottom portion of the bottom cover; at least one optical sheet on the light guide plate; a guide panel adjacent the guide plate and the optical sheet; and a fixing device. The fixing device includes a horizontal portion; and a side portion extending perpendicularly from the horizontal portion. The side portion includes second protrusion portions extending inward from an edge of the side portion and parallel to the horizontal portion, and supporting portions extending vertically from the side portion at distal ends of the side portion.

Abstract: A data processing device includes a compression circuit and a padding circuit. The compression circuit is configured to compare pairs of two contiguous bits within data composed of 2n bits (where n is a natural number), and compress the data based on a result of the comparison. The padding circuit is configured to generate transmission data of 2n bits by padding the compressed data with a dummy pad.

Abstract: Disclosed is a method and a system for realizing a Pay Per View (PPV) purchasing mechanism.

Abstract: Disclosed is a backlight unit and LCD device having a fixing device attached to a bottom cover and a guide panel to prevent the guide panel from shifting and detaching from the bottom cover. The backlight unit comprises a bottom cover having a bottom portion including a first hole, and a side portion having a second hole; a light guide plate on the bottom portion of the bottom cover; at least one optical sheet on the light guide plate; a guide panel adjacent the guide plate and the optical sheet; and a fixing device. The fixing device includes a horizontal portion; and a side portion extending perpendicularly from the horizontal portion. The side portion includes second protrusion portions extending inward from an edge of the side portion and parallel to the horizontal portion, and supporting portions extending vertically from the side portion at distal ends of the side portion.

Abstract: A stacked package including: a semiconductor substrate, a circuit layer formed over the semiconductor substrate, a bump formed over the circuit layer, a spare bump formed correspondingly to the bump and over the circuit layer, and configured for replacing the bump with the spare bump, a through electrode configuring to pass through the semiconductor substrate on a same line as the bump and electrically coupled the bump or the spare bump in response to a selection signal, and a spare through electrode configured to pass through the semiconductor substrate on a same line as the spare bump and electrically coupled with the bump or the spare bump in response to a selection signal. When a bump has failed, a vertical input/output line of the semiconductor chips is established by a spare bump corresponding to the failed bump through the selective signal routing.

Abstract: A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate.

Abstract: A data processing device includes a controller. The controller includes a compression circuit configured to compare a plurality of data groups, each of which has a first burst length and is transmitted in units of an input/output width, with a predetermined pattern, and perform data compression on the data groups based on a result of comparison. The controller further includes a compression data restructuring circuit configured to generate a transmission data group by restructuring the compressed data group to have a second burst length.

Abstract: A data processing device includes a compression circuit and a padding circuit. The compression circuit is configured to compare pairs of two contiguous bits within data composed of 2n bits (where n is a natural number), and compress the data based on a result of the comparison. The padding circuit is configured to generate transmission data of 2n bits by padding the compressed data with a dummy pad.

Abstract: A semiconductor device including a chip stack structure having a plurality of semiconductor chips, the semiconductor chips being stacked such that they are electrically connected using through-electrodes, and a support frame attached to a side surface of the chip stack structure.

Abstract: Disclosed are a flat panel type image display device of a clear borderless design without a case defining an external appearance of an image display device, and a method for manufacturing the same. The flat panel type image display device includes an image display panel to display an image, a panel guide including a panel fixing portion, to which the image display panel is attached, and a guide frame formed in a dual coupling structure, the panel fixing portion being configured to move together with the guide frame in at least one direction of x, y, and z-axis directions, and a bottom case formed to cover an opened back surface of the panel guide comprising a back surface of the image display panel, the bottom case being fixed to an inner side surface of the panel guide.

Abstract: A stacked package including: a semiconductor substrate, a circuit layer formed over the semiconductor substrate, a bump formed over the circuit layer, a spare bump formed correspondingly to the bump and over the circuit layer, and configured for replacing the bump with the spare bump, a through electrode configuring to pass through the semiconductor substrate on a same line as the bump and electrically coupled the bump or the spare bump in response to a selection signal, and a spare through electrode configured to pass through the semiconductor substrate on a same line as the spare bump and electrically coupled with the bump or the spare bump in response to a selection signal. When a bump has failed, a vertical input/output line of the semiconductor chips is established by a spare bump corresponding to the failed bump through the selective signal routing.

Abstract: A chip die including a first input/output (I/O) pad configured to transmit/receive an I/O signal of a memory cell array included in the chip die; a second I/O pad configured to, if a stacked chip die exists on the chip die, transmit/receive a via I/O signal of the stacked chip die, and configured to, if the stacked chip die does not exist on the chip die, transmit/receive a differential I/O signal of the chip die; and an I/O driver configured to receive an operation mode signal including information as to whether the stacked chip die exists on the chip die in such a manner that the second I/O pad is configured to transmit/receive the via I/O signal or the differential I/O signal.

Abstract: The present invention relates to an apparatus for manufacturing an EVA sheet for a solar cell sealant by uniformly arranging and melting heat adhesive resins, comprising: a powder supplying unit provided in the form of a container containing a heat-adhesive resin powder inside same and comprising a discharge outlet in the lower portion thereof; a powder-arranging roll which has a concave recess pattern on the surface thereof so as to contain the heat-adhesive resin powder and which is arranged so as to seal the discharge outlet; a circulation belt which circulates while passing through a lower portion of the powder-arranging roll; a heater unit which heats and melts the heat-adhesive resin powder applied onto the circulation belt; and a peel-off roll disposed at the rear end of the heater unit so as to separate the heat-adhesive resin powder sheet melted into a film from the circulation belt .

Abstract: A semiconductor memory device includes a plurality of first regions formed in a line-type and extending in a first direction, and a plurality of second regions and a plurality of third regions arranged between adjacent first regions in a zigzag manner.

Abstract: The present invention provides an EVA sheet for a solar cell sealing material comprising a thermal adhesion layer formed on an upper surface of a backsheet, wherein the thermal adhesion layer contains thermal adhesive resin powder including ethylene-based resin. The present invention further provides a method for manufacturing an EVA sheet for a solar cell sealing material, comprising: a step of laminating polyethyleneterephthalate to form a backsheet; a step of preparing thermal adhesive resin powder including ethylene-based resin; a step of scattering the thermal adhesive resin powder on the backsheet; and a step of hardening the scattered thermal adhesive resin powder to form a thermal adhesion layer.

Abstract: A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled.

Abstract: A semiconductor memory device includes a plurality of first regions formed in a line-type and extending in a first direction, and a plurality of second regions and a plurality of third regions arranged between adjacent first regions in a zigzag manner.

Abstract: A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled.